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ds07-16301-2e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos fr30 series mb91101/mb91101a n description the mb91101 is a standard single-chip microcontroller constructed around the 32-bit risc cpu (fr* family) core with abundant i/o resources and bus control functions optimized for high-performance/high-speed cpu processing for embedded controller applications. to support the vast memory space accessed by the 32-bit cpu, the mb91101 normally operates in the external bus access mode and executes instructions on the internal 1 kbyte cache memory and 2 kbytes ram for enhanced performance. the mb91101 is optimized for applications requiring high-performance cpu processing such as navigation systems, high-performance faxs and printer controllers. *: fr family stands for fujitsu risc controller. n features fr cpu ? 32-bit risc, load/store architecture, 5-stage pipeline ? operating clock frequency: internal 50 mhz/external 25 mhz (pll used at source oscillation 12.5 mhz) ? general purpose registers: 32 bits 16 ? 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle ? memory to memory transfer, bit processing, barrel shifter processing: optimized for embedded applications ? function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages ? register interlock functions, efficient assembly language coding ? branch instructions with delay slots: reduced overhead time in branch executions (continued) n pac k ag e 100-pin plastic lqfp (fpt-100p-m05) 100-pin plastic qfp (fpt-100p-m06)
mb91101/mb91101a 2 (continued) ? internal multiplier/supported at instruction level signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles ? interrupt (push pc and ps): 6 cycles, 16 priority levels external bus interface ? clock doubler: internal 50 mhz, external bus 25 mhz operation ? 25-bit address bus (32 mbytes memory space) ? 8/16-bit data bus ? basic external bus cycle: 2 clock cycles ? chip select outputs for setting down to a minimum memory block size of 64 kbytes: 6 ? interface supported for various memory technologies dram interface (area 4 and 5) ? automatic wait cycle insertion: flexible setting, from 0 to 7 for each area ? unused data/address pins can be configured us input/output ports ? little endian mode supported (select 1 area from area 1 to 5) dram interface ? 2 banks independent control (area 4 and 5) ? normal mode (double cas dram)/high-speed page mode (single cas dram)/hyper dram ? basic bus cycle: normally 5 cycles, 2-cycle access possible in high-speed page mode ? programmable waveform: automatic 1-cycle wait insertion to ras and cas cycles ?dram refresh cbr refresh (interval time configurable by 6-bit timer) self-refresh mode ? supports 8/9/10/12-bit column address width ? 2cas/1we, 2we/1cas selective cache memory ? 1-kbyte instruction cache memory ? 32 block/way, 4 entry(4 word)/block ? 2 way set associative ? lock function: for specific program code to be resident in cashe memory dma controller (dmac) ? 8 channels ? transfer incident/external pins/internal resource interrupt requests ? transfer sequence: step transfer/block transfer/burst transfer/continuous transfer ? transfer data length: 8 bits/16 bits/32 bits selective ? nmi/interrupt request enables temporary stop operation uart ? 3 independent channels ? full-duplex double buffer ? data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) ? asynchronous (start-stop system), clk-synchronized communication selective ? multi-processor mode ? internal 16-bit timer (u-timer) operating as a proprietary baud rate generator: generates any given baud rate ? use external clock can be used as a transfer clock ? error detection: parity, frame, overrun
3 mb91101/mb91101a (continued) 10-bit a/d converter (successive approximation conversion type) ? 10-bit resolution, 4 channels ? successive approximation type: conversion time of 5.6 m s at 25 mhz ? internal sample and hold circuit ? conversion mode: single conversion/scanning conversion/repeated conversion/stop conversion selective ? start: software/external trigger/internal timer selective 16-bit reload timer ? 3 channels ? internal clock: 2 clock cycle resolution, divide by 2/8/32 selective other interval timers ? 16-bit timer: 3 channels (u-timer) ? pwm timer: 4 channels ? watchdog timer: 1 channel bit search module first bit transition 1 or 0 from msb can be detected in 1 cycle interrupt controller ? external interrupt input: non-maskable interrupt (nmi ), normal interrupt 4 (int0 to int3) ? internal interrupt incident: uart, dma controller (dmac), a/d converter, u-timer and delayed interrupt module ? priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) others ? reset cause: power-on reset/hardware standby/watchdog timer/software reset/external reset ? low-power consumption mode: sleep mode/stop mode ? clock control gear function: operating clocks for cpu and peripherals are independently selective gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) however, operating frequency for peripherals is less than 25 mhz. ? packages: lqfp-100 and qfp-100 ? cmos technology (0.35 m m) ? power supply voltage 5 v: cpu power supply 5.0 v 10% (internal regulator) a/d power supply 2.7 v to 3.6 v 3 v: cpu power supply 2.7 v to 3.6 v (without internal regulator) a/d power supply 2.7 v to 3.6 v
mb91101/mb91101a 4 n pin assignment (fpt-100p-m05) (top view) 1 cs1l/pb5/dreq2 cs1h/pb6/dack2 dw1/pb7 v cc 3 clk/pa6 cs5/pa5 cs4/pa4 cs3/pa3/eop1 cs2/pa2 cs1/pa1 cs0 nmi hst rst v ss md0 md1 md2 rdy/p80 bgrnt/p81 brq/p82 rd wr0 wr1/p85 d16/p20 2 3 4 5 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 55 54 53 52 51 an3 an2 an1 an0 av ss /avrl avrh av cc a24/eop0 a23/p67 a22/p66 v ss a21/p65 a20/p64 a19/p63 a18/p62 a17/p61 a16/p60 a15 a14 a13 a12 a11 a10 a09 a08 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 ras1/pb4/eop2 dw0/pb3 cs0h/pb2 cs0l/pb1 ras0/pb0 int0/pe0 int1/pe1 v cc 5 x0 x1 v ss int2/sc1/pe2 int3/sc2/pe3 dreq0/pe4 dreq1/pe5 dack0/pe6 dack1/pe7 ocpa0/pf7/atg so2/ocpa2/pf6 si2/ocpa1/pf5 so1/trg3/pf4 si1/trg2/pf3 sc0/ocpa3/pf2 so0/trg1/pf1 si0/trg0/pf0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 d24 d25 d26 d27 d28 d29 d30 v ss d31 a00 v cc 5 a01 a02 a03 a04 a05 a06 a07
5 mb91101/mb91101a (fpt-100p-m06) 1 cs0h/pb2 80 2 dw0/pb3 79 3 ras1/pb4/eop2 78 4 cs1l/pb5/dreq2 77 5 cs1h/pb6/dack2 76 6 dw1/pb7 75 7 v cc 3 74 8 clk/pa6 73 9 cs5/pa5 72 10 cs4/pa4 71 11 cs3/pa3/eop1 70 12 cs2/pa2 69 13 cs1/pa1 68 14 cs0 67 15 nmi 66 16 hst 65 17 rst 64 18 v ss 63 19 md0 62 20 md1 61 21 md2 60 22 rdy/p80 59 23 bgrnt/p81 58 24 brq/p82 57 25 rd 56 26 wr0 55 27 wr1/p85 54 28 d16/p20 53 29 d17/p21 52 30 d18/p22 51 so0/trg1/pf1 si0/trg0/pf0 an3 an2 an1 an0 av ss /avrl avrh av cc a24/eop0 a23/p67 a22/p66 v ss a21/p65 a20/p64 a19/p63 a18/p62 a17/p61 a16/p60 a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cs0l/pb1 ras0/pb0 int0/pe0 int1/pe1 v cc 5 x0 x1 v ss int2/sc1/pe2 int3/sc2/pe3 dreq0/pe4 dreq1/pe5 dack0/pe6 dack1/pe7 ocpa0/pf7/atg so2/ocpa2/pf6 si2/ocpa1/pf5 so1/trg3/pf4 si1/trg2/pf3 sc0/ocpa3/pf2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 d24 d25 d26 d27 d28 d29 d30 v ss d31 a00 v cc 5 a01 a02 a03 a04 (top view)
mb91101/mb91101a 6 n pin description *1: fpt-100p-m05 (continued) *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 25 to 32 28 to 35 d16 to d23 c bit 16 to bit 23 of external data bus p20 to p27 can be configured as i/o ports when external data bus width is set to 8-bit. 33 to 39, 41 36 to 42, 44 d24 to d30, d31 c bit 24 to bit 31 of external data bus 42, 44 to 58 45, 47 to 61 a00, a01 to a15 f bit 00 to bit 15 of external address bus 59 to 64, 66, 67 62 to 67, 69, 70 a16 to a21, a22, a23 f bit 16 to bit 23 of external address bus p60 to p65, p66, p67 can be configured as i/o ports when not used as address bus. 68 71 a24 l bit 24 of external address bus eop0 can be configured as dmac eop output (ch. 0) when dmac eop output is enabled. 19 22 rdy c external ready input inputs 0 when bus cycle is being executed and not completed. p80 can be configured as a port when rdy is not used. 20 23 bgrnt f external bus release acknowledge output outputs l level when external bus is released. p81 can be configured as a port when bgrnt is not used. 21 24 brq c external bus release request input inputs 1 when release of external bus is required. p82 can be configured as a port when brq is not used. 22 25 rd l read strobe output pin for external bus 23 26 wr0 l write strobe output pin for external bus relation between control signals and effective byte locations is as follows: note: wr1 is hi-z during resetting. attach an external pull-up resister when using at 16-bit bus width. 24 27 wr1 f p85 can be configured as a port when wr1 is not used. 16-bit bus width 8-bit bus width d15 to d08 wr0 wr0 d07 to d00 wr1 (i/o port enabled)
7 mb91101/mb91101a *1: fpt-100p-m05 (continued) *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 11 14 cs0 l chip select 0 output (l active) 10 13 cs1 f chip select 1 output (l active) pa1 can be configured as a port when cs1 is not used. 912cs2 f chip select 2 output (l active) pa2 can be configured as a port when cs2 is not used. 811cs3 f chip select 3 output (l active) pa3 can be configured as a port when cs3 and eop1 are not used. eop1 eop output pin for dmac (ch. 1) this function is available when eop output for dmac is enabled. 710cs4 f chip select 4 output (l active) pa4 can be configured as a port when cs4 is not used. 69cs5 f chip select 5 output (l active) pa5 can be configured as a port when cs5 is not used. 5 8 clk f system clock output outputs clock signal of external bus operating frequency. pa6 can be configured as a port when clk is not used. 96 99 ras0 f ras output for dram bank 0 refer to the dram interface for details. pb0 can be configured as a port when ras0 is not used. 97 100 cs0l f casl output for dram bank 0 refer to the dram interface for details. pb1 can be configured as a port when cs0l is not used. 98 1 cs0h f cash output for dram bank 0 refer to the dram interface for details. pb2 can be configured as a port when cs0h is not used. 99 2 dw0 fwe output for dram bank 0 (l active) refer to the dram interface for details. pb3 can be configured as a port when dw0 is not used. 100 3 ras1 f ras output for dram bank 1 refer to the dram interface for details. pb4 can be configured as a port when ras1 and eop2 are not used. eop2 dmac eop output (ch. 2) this function is available when dmac eop output is enabled.
mb91101/mb91101a 8 *1: fpt-100p-m05 (continued) *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 1 4 cs1l f casl output for dram bank 1 refer to the dram interface for details. pb5 can be configured as a port when cs1l and dreq2 are not used. dreq2 external transfer request input pin for dma this pin is used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 2 5 cs1h f cash output for dram bank 1 refer to the dram interface for details. pb6 can be configured as a port when cs1h and dack2 are not used. dack2 external transfer request acknowledge output pin for dmac (ch. 2) this function is available when transfer request output for dmac is enabled. 36dw1 fwe output for dram bank 1 (l active) refer to the dram interface for details. pb7 can be configured as a port when dw1 is not used. 16 to 18 19 to 21 md0 to md2 g mode pins 0 to 2 mcu basic operation mode is set by these pins. directly connect these pins with v cc or v ss for use. 92 95 x0 a clock (oscillator) input 91 94 x1 a clock (oscillator) output 14 17 rst b external reset input 13 16 hst h hardware standby input (l active) 12 15 nmi h nmi (non-maskable interrupt pin) input (l active) 95, 94 98, 97 int0, int1 f external interrupt request input pins these pins are used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. pe0, pe1 can be configured as a i/o port when int0, int1 are not used. 89 92 int2 f external interrupt request input pin this pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. sc1 clock i/o pin for uart1 clock output is available when clock output of uart1 is enabled. pe2 can be configured as a i/o port when int2 and sc1 are not used. this function is available when uart1 clock output is disabled.
9 mb91101/mb91101a *1: fpt-100p-m05 (continued) *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 88 91 int3 f external interrupt request input pin this pin is used for input during corresponding interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. sc2 uart2 clock i/o pin clock output is available when uart2 clock output is enabled. pe3 can be configured as a i/o port when int3 and sc2 are not used. this function is available when uart2 clock output is disabled. 87, 86 90, 89 dreq0, dreq1 f external transfer request input pins for dma these pins are used for input when external trigger is selected to cause dmac operation, and it is necessary to disable output for other functions from these pins unless such output is made intentionally. pe4, pe5 can be configured as a i/o port when dreq0, dreq1 are not used. 85 88 dack0 f external transfer request acknowledge output pin for dmac (ch. 0) this function is available when transfer request output for dmac is enabled. pe6 can be configured as a i/o port when dack0 is not used. this function is available when transfer request acknowledge output for dmac or dack0 output is disabled. 84 87 dack1 f external transfer request acknowledge output pin for dmac (ch. 1) this function is available when transfer request output for dmac is enabled. pe7 can be configured as a i/o port when dack1 is not used. this function is available when transfer request output for dmac or dack1 output is disabled. 76 79 si0 f uart0 data input pin this pin is used for input during uart0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. trg0 pwm timer external trigger input pin this pin is used for input during pwm timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pf0 can be configured as a i/o port when si0 and trg0 are not used.
mb91101/mb91101a 10 *1: fpt-100p-m05 (continued) *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 77 80 so0 f uart0 data output pin this function is available when uart0 data output is enabled. trg1 pwm timer external trigger input pin this function is available when serial data output of pf1, uart0 are disabled. pf1 can be configured as a i/o port when so0 and trg1 are not used. this function is available when serial data output of uart0 is disabled. 78 81 sc0 f uart0 clock i/o pin clock output is available when uart0 clock output is enabled. ocpa3 pwm timer output pin this function is available when pwm timer output is enabled. pf2 can be configured as a i/o port when sc0 and ocpa3 are not used. this function is available when uart0 clock output is disabled. 79 82 si1 f uart1 data input pin this pin is used for input during uart1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. trg2 pwm timer external trigger input pin this pin is used for input during pwm timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. pf3 can be configured as a i/o port when si1 and trg2 are not used. 80 83 so1 f uart1 data output pin this function is available when uart1 data output is enabled. trg3 pwm timer external trigger input pin this function is available when pf4, uart1 data outputs are disabled. pf4 can be configured as a i/o port when so1 and trg3 are not used. this function is available when uart1 data output is disabled. 81 84 si2 f uart2 data input pin this pin is used for input during uart2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. ocpa1 pwm timer output pin this function is available when pwm timer output is enabled. pf5 can be configured as a i/o port when si2 and ocpa1 are not used.
11 mb91101/mb91101a (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 note: in most of the above pins, i/o port and resource i/o are multiplexed e.g. p82 and brq. in case of conflict between output of i/o port and resource i/o, priority is always given to the output of resource i/o. pin no. pin name circuit type function lqfp* 1 qfp* 2 82 85 so2 f uart2 data output pin this function is available when uart2 data output is enabled. ocpa2 pwm timer output pin this function is available when pwm timer output is enabled. pf6 can be configured as a i/o port when so2 and ocpa2 are not used. this function is available when uart2 data output is disabled. 83 86 ocpa0 f pwm timer output pin this function is available when pwm timer output is enabled. pf7 can be configured as a i/o port when ocpa0 and atg are not used. this function is available when pwm timer output is disabled. at g external trigger input pin for a/d converter this pin is used for input when external trigger is selected to cause a/d converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. 72 to 75 75 to 78 an0 to an3 d analog input pins of a/d converter this function is available when aic register is set to specify analog input mode. 69 72 av cc power supply pin (v cc ) for a/d converter 70 73 avrh reference voltage input (high) for a/d converter make sure to turn on and off this pin with potential of avrh or more applied to v cc . 71 74 av ss / avrl power supply pin (v ss ) for a/d converter and reference voltage input pin (low) 43, 93 46, 96 v cc 5 5 v power supply pin (v cc ) for digital circuit always two pins must be connected to the power supply (connect to 3 v power supply when operating at 3 v). 47v cc 3 bypass capacitor pin for internal capacitor. also connect this pin to 3 v power supply when operating at 3 v. 15, 40, 65, 90 18, 43, 68, 93 v ss earth level (v ss ) for digital circuit
mb91101/mb91101a 12 n dram control pin pin name data bus 16-bit mode data bus 8-bit mode remarks 2cas/1wr mode 1cas/2wr mode ras0 area 4 ras area 4 ras area 4 ras correspondence of l h to lower address 1 bit (a0) in data bus 16- bit mode l: 0 h: 1 casl: cas which a0 corresponds to 0 area cash: cas which a0 corresponds to 1 area wel : we which a0 corresponds to 0 area weh :we which a0 corresponds to 1 area ras1 area 5 ras area 5 ras area 5 ras cs0l area 4 casl area 4 cas area 4 cas cs0h area 4 cash area 4 wel area 4 cas cs1l area 5 casl area 5 cas area 5 cas cs1h area 5 cash area 5 wel area 5 cas cw0 area 4 we area 4 weh area 4 we dw1 area 5 we area 5 weh area 5 we
13 mb91101/mb91101a n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistance 1 m w approx. with standby control b ? cmos level hysteresis input without standby control with pull-up resistance c ? cmos level i/o with standby control d ? analog input x1 x0 standby control signal clock input v ss p-ch r p-ch n-ch v cc digital input r standby control signal digital input digital output digital output p-ch n-ch r analog input digital output digital output p-ch n-ch
mb91101/mb91101a 14 (continued) type circuit remarks e ? n-ch open-drain output ? cmos level input with standby control f ? cmos level output ? cmos level hysteresis input with standby control g ? cmos level input without standby control h ? cmos level hysteresis input without standby control r p-ch n-ch standby control signal digital input digital output r p-ch n-ch standby control signal digital input digital output digital output r p-ch n-ch digital input r p-ch n-ch digital input
15 mb91101/mb91101a (continued) type circuit remarks i ? cmos level output ? cmos level hysteresis input without standby control j ? cmos level output ? ttl level input with standby control k ? cmos level input/output with standby control ? large current drive l ? cmos level output r p-ch n-ch digital input digital output digital output r p-ch n-ch ttl standby control signal digital input digital output digital output r p-ch n-ch standby control signal digital input digital output digital output p-ch n-ch digital output digital output
mb91101/mb91101a 16 n handling devices 1. preventing latchup in cmos ics, applying voltage higher than v cc or lower than v ss to input/output pin or applying voltage over rating across v cc and v ss may cause latchup. this phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. make sure to prevent the voltage from exceeding the maximum rating. take care that the analog power supply (av cc , avr) and the analog input do not exceed the digital power supply (v cc ) when the analog power supply turned on or off. 2. treatment of unused pins unused pins left open may cause malfunctions. make sure to connect them to pull-up or pull-down resistors. 3. external reset input it takes at least 5 machine cycle to input l level to the rst pin and to ensure inner reset operation properly. 4. remarks for external clock operation when external clock is selected, supply it to x0 pin generally, and simultaneously the opposite phase clock to x0 must be supplied to x1 pin. however, in this case the stop mode must not be used (because x1 pin stops at h output in stop mode). and can be used to supply only to x0 pin with 5 v power supply at 12.5 mhz and less than. x0 x1 open mb91101 x0 x1 mb91101 using an external clock (normal) note: can not be used stop mode (oscillation stop mode). using an external clock (can be used at 12.5 mhz and less than.) (5 v power supply only) ? using an external clock
17 mb91101/mb91101a 5. power supply pins when there are several v cc and v ss pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. to further reduce the risk of malfunctions, to prevent emi radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all v cc and v ss pins to the power supply or gnd. it is preferred to connect v cc and v ss of mb91101 to power supply with minimal impedance possible. it is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 m f between v cc and v ss at a position as close as possible to mb91101. mb91101 has an internal regulator. when using with 5 v power supply, supply 5 v to v cc 5 pin and make sure to connect about 0.1 m f bypass capacitor to v cc 3 pin for regulator. and another 3 v power supply is needed for the a/d convertor. when using with 3 v power supply, connect both v cc 5 pin and v cc 3 pin to the 3 v power supply. 6. crystal oscillator circuit noises around x0 and x1 pins may cause malfunctions of mb91101. in designing the pc board, layout x0, x1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. it is strongly recommended to design pc board so that x1 and x0 pins are surrounded by grounding area for stable operation. 7. turning-on sequence of a/d converter power supply and analog input make sure to turn on the digital power supply (v cc ) before turning on the a/d converter (av cc , avrh) and applying voltage to analog input (an0 to an3). make sure to turn off digital power supply after power supply to a/d converters and analog inputs have been switched off. (there are no such limitations in turning on power supplies. analog and digital power supplies may be turned on simultaneously.) make sure that avrh never exceeds av cc when turning on/off power supplies. 8. treatment of n.c. pins make sure to leave n.c. pins open. ? connecting to a power supply v cc 5 av cc avrh av ss v ss v cc 3 5 v gnd [using with 5 v power supply] v cc 5 av cc avrh av ss v ss v cc 3 3 v 3 v gnd [using with 3 v power supply] about 0.1 m f
mb91101/mb91101a 18 9. fluctuation of power supply voltage warranty range for normal operation against fluctuation of power supply voltage v cc is as given in rating. however, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. it is recommended to make every effort to stabilize the power supply voltage to ic. it is also recommended that by controlling power supply as a reference of stabilizing, v cc ripple fluctuation (p-p value) at the commercial frequency (50 hz to 60 hz) should be less than 10% of the standard v cc value and the transient regulation should be less than 0.1 v/ms at instantaneous deviation like turning off the power supply. 10. mode setting pins (md0 to md2) connect mode setting pins (md0 to md2) directly to v cc or v ss . arrange each mode setting pin and v cc or v ss patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. 11. internal dc regulator internal dc regulator stops in stop mode. when the regulator stops owing to the increase of inner leakage current (icch) in stop mode, malfunction caused by noise or any troubles about power supply in normal operation, the internal 3 v power supply voltage may decrease less than the warranty range for normal operation. so when using the internal regulator and stop mode with 5 v power supply, never fail to support externally so that 3 v power supply voltage might not decrease. however, even in such a case, the internal regulator can be restarted by inputting the reset procedure. (in this case, set the reset to l level within the oscillation stabilizing waiting time.) 12. turning on the power supply when turning on the power supply, never fail to start from setting the rst pin to l level. and after the power supply voltage goes to v cc level, at least after ensuring the time for 5 machine cycle, then set to h level. 13. pin condition at turning on the power supply the pin condition at turning on the power supply is unstable. the circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation of the internal regulator becomes stable. so it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5 mhz. take care that the pin condition may be output condition at initial unstable condition. (with the mb91101a, however, initalization can be achieved in less than about 42 ms after turning on the internal power supply by maintaining the rst pin at "l" level.) v cc 5 v cc 3 v ss 3.6 k w 6.8 k w 0.1 m f approx. 5 v ? using stop mode with 5 v power supply
19 mb91101/mb91101a 14. source oscillation input at turning on the power supply at turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. 15. hardware stand-by at turning on the power supply when turning on the power supply with the hst pin being set to l level, the hardware doesnt stand by. however the hst pin becomes available after the reset cancellation, the hst pin must once be back to h level. 16. power on reset make sure to make power on reset at turning on the power supply or returning on the power supply when the power supply voltage is below the warranty range for normal operation.
mb91101/mb91101a 20 n block diagram an0 to an3 av cc av ss /avrl avrh bit search module instruction cache (1 kbyte) d-bus (32 bits) i-bus (16 bits) c-bus (32 bits) r-bus (16 bits) clock control unit (watchdog timer) interrupt control unit 10-bit a/d converter (4 ch.) reload timer (3 ch.) port bus converter (32 bits ? 16 bits) dram controller port 0 to port b uart (3 ch.) (baud rate timer) bus controller dma controller (dmac) (8 ch.) bus converter (harvard ? princeton) ram (2 kbytes) pwm timer (4 ch.) fr cpu x0 x1 rst hst dreq0 to dreq2 dack0 to dack2 eop0 to eop2 d16 to d31 a00 to a24 rd wr0, wr1 rdy clk cs0 to cs5 brq bgrnt si0 to si2 so0 to so2 sc0 to sc2 ocpa0 to ocpa3 trg0 to trg3 int0 to int3 nmi atg 4 4 3 3 3 4 4 ras0 ras1 cs0l cs0h cs1l cs1h dw0 dw1 6 3 3 2 25 16 md0 to md2, p20 to p27, p60 to p67, p80 to p82, p85, pa1 to pa6, pb0 to pb7, pe0 to pe7, pf0 to pf7, v cc 3, v cc 5, v ss other pins note: pins are display for functions (actually some pins are multiplexer). when using realos, time control should be done by using external interrupt or inner timer.
21 mb91101/mb91101a n cpu core 1. memory space the fr family has a logical address space of 4 gbytes (2 32 bytes) and the cpu linearly accesses the memory space. ? direct addressing area the following areas on the memory space are assigned to direct addressing area for i/o. in these areas, an address can be specified in a direct operand of a code. direct areas consists of the following areas dependent on accessible data sizes. byte data access: 000 h to 0ff h half word data access: 000 h to 1ff h word data access: 000 h to 3ff h ? memory space i/o area i/o area access inhibited access inhibited external area direct addressing area see n i/o map 0000 0000 h 0000 0400 h 0000 0800 h 0001 0000 h ffff ffff h external rom/external bus mode embedded ram 0000 1800 h 0000 1000 h address
mb91101/mb91101a 22 2. registers the fr family has two types of registers; dedicated registers embedded on the cpu and general-purpose registers on memory. ? dedicated registers program counter (pc): 32-bit length, indicates the location of the instruction to be executed. program status (ps): 32-bit length, register for storing register pointer or condition codes table base register (tbr): holds top address of vector table used in eit (exceptional/interrupt/trap) processing. return pointer (rp): holds address to resume operation after returning from a subroutine. system stack pointer (ssp): indicates system stack space. user's stack pointer (usp): indicates users stack space. multiplication/division result register (mdh/mdl): 32-bit length, register for multiplication/division ? program status (ps) the ps register is for holding program status and consists of a condition code register (ccr), a system condition code register (scr) and a interrupt level mask register (ilm). pc ps tbr rp ssp usp mdh mdl initial value program counter program status table base register return pointer system stack pointer users stack pointer multiplication/division result register xxxx xxxx h indeterminate 000f fc00 h xxxx xxxx h indeterminate 0000 0000 h xxxx xxxx h indeterminate xxxx xxxx h indeterminate xxxx xxxx h indeterminate 32 bits ilm4 ilm3 ilm2 ilm1 ilm0 d1 d0 t s zc v n i 31 to 21 20 19 18 17 11 to 15 16 10 9 8 7 5 620 1 3 4 ilm scr ccr ps
23 mb91101/mb91101a ? condition code register (ccr) s-flag: specifies a stack pointer used as r15. i-flag: controls user interrupt request enable/disable. n-flag: indicates sign bit when division result is assumed to be in the 2s complement format. z-flag: indicates whether or not the result of division was 0. v-flag: assumes the operand used in calculation in the 2s complement format and indicates whether or not overflow has occurred. c-flag: indicates if a carry or borrow from the msb has occurred. ? system condition code register (scr) t-flag: specifies whether or not to enable step trace trap. ? interrupt level mask register (ilm) ilm4 to ilm0: register for holding interrupt level mask value. the value held by this register is used as a level mask. when an interrupt request issued to the cpu is higher than the level held by ilm, the interrupt request is accepted. ilm4 ilm3 ilm2 ilm1 ilm0 interrupt level high-low 00000 0 high : : : : 01000 15 : : : : 11111 31 low
mb91101/mb91101a 24 n general-purpose registers r0 to r15 are general-purpose registers embedded on the cpu. these registers functions as an accumulator and a memory access pointer (field for indicating address). of the above 16 registers, following registers have special functions. to support the special functions, part of the instruction set has been sophisticated to have enhanced functions. r13: virtual accumulator (ac) r14: frame pointer (fp) r15: stack pointer (sp) upon reset, values in r0 to r14 are not fixed. value in r15 is initialized to be 0000 0000 h (ssp value). ? register bank structure r0 r1 r12 r13 r14 r15 ac (accumulator) fp (frame pointer) sp (stack pointer) 32 bits : : initial value xxxx xxxx h : : : : : : : : : : : xxxx xxxx h 0000 0000 h
25 mb91101/mb91101a n setting mode 1. pin ? mode setting pins and modes * : mb91101 does not support single-chip mode. 2. registers ? mode setting registers (modr) and modes ? bus mode setting bits and functions note: because of without internal rom, mb91101 allows 10 b setting value only. mode setting pins mode name reset vector access area external data bus width bus mode md2 md1 md0 0 0 0 external vector mode 0 external 8 bits external rom/external bus mode 0 0 1 external vector mode 1 external 16 bits 0 1 0 inhibited 0 1 1 internal vector mode internal (mode register) single-chip mode* 1 inhibited m1 m0 functions note 0 0 single-chip mode 0 1 internal rom/external bus mode 1 0 external rom/external bus mode 1 1 inhibited m1 m0 ** * *** address 0000 07ff h bus mode setting bit w : write only x : indeterminate * : always write 0 except for m1 and m0. initial value xxxx xxxx b access w
mb91101/mb91101a 26 n i/o map (continued) address register name (abbreviated) register name read/write initial value 0000 h (vacancy) 0001 h pdr2 port 2 data register r/w x x x x x x x x b 0002 h to 0004 h (vacancy) 0005 h pdr6 port 6 data register r/w x x x x x x x x b 0006 h (vacancy) 0007 h 0008 h pdrb port b data register r/w x x x x x x x x b 0009 h pdra port a data register r/w C x x x x x x C b 000a h (vacancy) 000b h pdr8 port 8 data register r/w C C x C C x x x b 000c h to 0011 h (vacancy) 0012 h pdre port e data register r/w x x x x x x x x b 0013 h pdrf port f data register r/w xxxxxxxx b 0014 h to 001b h (vacancy) 001c h ssr0 serial status register 0 r/w 0 0 0 0 1 C 0 0 b 001d h sidr0/sodr0 serial input register 0/serial output register 0 r/w x x x x x x x x b 001e h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b 001f h smr0 serial mode register 0 r/w 0 0 C C 0 C 0 0 b 0020 h ssr1 serial status register 1 r/w 0 0 0 0 1 C 0 0 b 0021 h sidr1/sodr1 serial input register 1/serial output register 1 r/w x x x x x x x x b 0022 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 0023 h smr2 serial mode register 1 r/w 0 0 C C 0 C 0 0 b 0024 h ssr2 serial status register 2 r/w 0 0 0 0 1 C 0 0 b 0025 h sidr2/sodr2 serial input register 2/serial output register 2 r/w x x x x x x x x b 0026 h scr2 serial control register 2 r/w 0 0 0 0 0 1 0 0 b 0027 h smr2 serial mode register 2 r/w 0 0 C C 0 C 0 0 b
27 mb91101/mb91101a (continued) address register name (abbreviated) register name read/write initial value 0028 h tmrlr0 16-bit reload register ch. 0 w xxxxxxxx b 0029 h xxxxxxxx b 002a h tmr0 16-bit timer register ch. 0 r xxxxxxxx b 002b h xxxxxxxx b 002c h (vacancy) 002d h 002e h tmcsr0 16-bit reload timer control status register ch. 0 r/w CCCC0000 b 002f h 00000000 b 0030 h tmrlr1 16-bit reload register ch. 1 w xxxxxxxx b 0031 h xxxxxxxx b 0032 h tmr1 16-bit timer register ch. 1 r xxxxxxxx b 0033 h xxxxxxxx b 0034 h (vacancy) 0035 h 0036 h tmcsr1 16-bit reload timer control status register ch. 1 r/w CCCC0000 b 0037 h 00000000 b 0038 h adcr a/d converter data register r CCCCCCxx b 0039 h xxxxxxxx b 003a h adcs a/d converter control status register r/w 00000000 b 003b h 00000000 b 003c h tmrlr2 16-bit reload register ch. 2 w xxxxxxxx b 003d h xxxxxxxx b 003e h tmr2 16-bit timer register ch. 2 r xxxxxxxx b 003f h xxxxxxxx b 0040 h (vacancy) 0041 h 0042 h tmcsr2 16-bit reload timer control status register ch. 2 r/w CCCC0000 b 0043 h 00000000 b 0044 h to 0077 h (vacancy)
mb91101/mb91101a 28 (continued) address register name (abbreviated) register name read/write initial value 0078 h utim0/utimr0 u-timer register ch. 0/reload register ch. 0 r/w 00000000 b 0079 h 00000000 b 007a h (vacancy) 007b h utimc0 u-timer control register ch. 0 r/w 0 C C 0 0 0 0 1 b 007c h utim1/utimr1 u-timer register ch. 1/reload register ch. 1 r/w 00000000 b 007d h 00000000 b 007e h (vacancy) 007f h utimc1 u-timer control register ch. 1 r/w 0 C C 0 0 0 0 1 b 0080 h utim2/utimr2 u-timer register ch. 2/reload register ch. 0 r/w 00000000 b 0081 h 00000000 b 0082 h (vacancy) 0083 h utimc2 u-timer control register ch. 2 r/w 0 C C 0 0 0 0 1 b 0084 h to 0093 h (vacancy) 0094 h eirr external interrupt cause register r/w 0 0 0 0 0 0 0 0 b 0095 h enir interrupt enable register r/w 0 0 0 0 0 0 0 0 b 0096 h to 0098 h (vacancy) 0099 h elvr external interrupt request level setting register r/w 00000000 b 009a h to 00d1 h (vacancy) 00d2 h ddre port e data direction register w 0 0 0 0 0 0 0 0 b 00d3 h ddrf port f data direction register w 0 0 0 0 0 0 0 0 b 00d4 h to 00db h (vacancy) 00dc h gcn1 general control register 1 r/w 00110010 b 00dd h 00010000 b 00de h (vacancy) 00df h gcn2 general control register 2 r/w 0 0 0 0 0 0 0 0 b
29 mb91101/mb91101a (continued) address register name (abbreviated) register name read/write initial value 00e0 h ptmr0 ch. 0 timer register r 11111111 b 00e1 h 11111111 b 00e2 h pcsr0 ch. 0 cycle setting register w xxxxxxxx b 00e3 h xxxxxxxx b 00e4 h pdut0 ch. 0 duty setting register w xxxxxxxx b 00e5 h xxxxxxxx b 00e6 h pcnh0 ch. 0 control status register h r/w 0 0 0 0 0 0 0 C b 00e7 h pcnl0 ch. 0 control status register l r/w 0 0 0 0 0 0 0 0 b 00e8 h ptmr1 ch. 1 timer register r 11111111 b 00e9 h 11111111 b 00ea h pcsr1 ch. 1 cycle setting register w xxxxxxxx b 00eb h xxxxxxxx b 00ec h pdut1 ch. 1 duty setting register w xxxxxxxx b 00ed h xxxxxxxx b 00ee h pcnh1 ch. 1 control status register h r/w 0 0 0 0 0 0 0 C b 00ef h pcnl1 ch. 1 control status register l r/w 0 0 0 0 0 0 0 0 b 00f0 h ptmr2 ch. 2 timer register r 11111111 b 00f1 h 11111111 b 00f2 h pcsr2 ch. 2 cycle setting register w xxxxxxxx b 00f3 h xxxxxxxx b 00f4 h pdut2 ch. 2 duty setting register w xxxxxxxx b 00f5 h xxxxxxxx b 00f6 h pcnh2 ch. 2 control status register h r/w 0 0 0 0 0 0 0 C b 00f7 h pcnl2 ch. 2 control status register l r/w 0 0 0 0 0 0 0 0 b 00f8 h ptmr3 ch. 3 timer register r 11111111 b 00f9 h 11111111 b 00fa h pcsr3 ch. 3 cycle setting register w xxxxxxxx b 00fb h xxxxxxxx b 00fc h pdut3 ch. 3 duty setting register w xxxxxxxx b 00fd h xxxxxxxx b 00fe h pcnh3 ch. 3 control status register h r/w 0 0 0 0 0 0 0 C b 00ff h pcnl3 ch. 3 control status register l r/w 0 0 0 0 0 0 0 0 b
mb91101/mb91101a 30 (continued) address register name (abbreviated) register name read/write initial value 0100 h to 01ff h (vacancy) 0200 h dpdp dmac parameter descriptor pointer r/w xxxxxxxx b 0201 h xxxxxxxx b 0202 h xxxxxxxx b 0203 h x0000000 b 0204 h dacsr dmac control status register r/w 00000000 b 0205 h 00000000 b 0206 h 00000000 b 0207 h 00000000 b 0208 h datcr dmac pin control register r/w xxxxxxxx b 0209 h xxxx0 0 0 0 b 020a h xxxx0 0 0 0 b 020b h xxxx0 0 0 0 b 020c h to 03e3 h (vacancy) 03e4 h ichcr instruction cache control register r/w CCCCCCCC b 03e5 h CCCCCCCC b 03e6 h CCCCCCCC b 03e7 h CC000000 b 03e8 h to 03ef h (vacancy) 03f0 h bsd0 bit search module 0-detection data register w xxxxxxxx b 03f1 h xxxxxxxx b 03f2 h xxxxxxxx b 03f3 h xxxxxxxx b 03f4 h bsd1 bit search module 1-detection data register r/w xxxxxxxx b 03f5 h xxxxxxxx b 03f6 h xxxxxxxx b 03f7 h xxxxxxxx b
31 mb91101/mb91101a (continued) address register name (abbreviated) register name read/write initial value 03f8 h bsdc bit search module transition-detection data register w xxxxxxxx b 03f9 h xxxxxxxx b 03fa h xxxxxxxx b 03fb h xxxxxxxx b 03fc h bsrr bit search module detection result register r xxxxxxxx b 03fd h xxxxxxxx b 03fe h xxxxxxxx b 03ff h xxxxxxxx b 0400 h icr00 interrupt control register 0 r/w C C C 1 1 1 1 1 b 0401 h icr01 interrupt control register 1 r/w C C C 1 1 1 1 1 b 0402 h icr02 interrupt control register 2 r/w C C C 1 1 1 1 1 b 0403 h icr03 interrupt control register 3 r/w C C C 1 1 1 1 1 b 0404 h icr04 interrupt control register 4 r/w C C C 1 1 1 1 1 b 0405 h icr05 interrupt control register 5 r/w C C C 1 1 1 1 1 b 0406 h icr06 interrupt control register 6 r/w C C C 1 1 1 1 1 b 0407 h icr07 interrupt control register 7 r/w C C C 1 1 1 1 1 b 0408 h icr08 interrupt control register 8 r/w C C C 1 1 1 1 1 b 0409 h icr09 interrupt control register 9 r/w C C C 1 1 1 1 1 b 040a h icr10 interrupt control register 10 r/w C C C 1 1 1 1 1 b 040b h icr11 interrupt control register 11 r/w C C C 1 1 1 1 1 b 040c h icr12 interrupt control register 12 r/w C C C 1 1 1 1 1 b 040d h icr13 interrupt control register 13 r/w C C C 1 1 1 1 1 b 040e h icr14 interrupt control register 14 r/w C C C 1 1 1 1 1 b 040f h icr15 interrupt control register 15 r/w C C C 1 1 1 1 1 b 0410 h icr16 interrupt control register 16 r/w C C C 1 1 1 1 1 b 0411 h icr17 interrupt control register 17 r/w C C C 1 1 1 1 1 b 0412 h icr18 interrupt control register 18 r/w C C C 1 1 1 1 1 b 0413 h icr19 interrupt control register 19 r/w C C C 1 1 1 1 1 b 0414 h icr20 interrupt control register 20 r/w C C C 1 1 1 1 1 b 0415 h icr21 interrupt control register 21 r/w C C C 1 1 1 1 1 b 0416 h icr22 interrupt control register 22 r/w C C C 1 1 1 1 1 b
mb91101/mb91101a 32 (continued) address register name (abbreviated) register name read/write initial value 0417 h icr23 interrupt control register 23 r/w C C C 1 1 1 1 1 b 0418 h icr24 interrupt control register 24 r/w C C C 1 1 1 1 1 b 0419 h icr25 interrupt control register 25 r/w C C C 1 1 1 1 1 b 041a h icr26 interrupt control register 26 r/w C C C 1 1 1 1 1 b 041b h icr27 interrupt control register 27 r/w C C C 1 1 1 1 1 b 041c h icr28 interrupt control register 28 r/w C C C 1 1 1 1 1 b 041d h icr29 interrupt control register 29 r/w C C C 1 1 1 1 1 b 041e h icr30 interrupt control register 30 r/w C C C 1 1 1 1 1 b 041f h icr31 interrupt control register 31 r/w C C C 1 1 1 1 1 b 042f h icr47 interrupt control register 47 r/w C C C 1 1 1 1 1 b 0430 h dicr delayed interrupt control register r/w C C C C C C C 0 b 0431 h hrcl hold request cancel request level setting register r/w CCC11111 b 0432 h to 047f h (vacancy) 0480 h rsrr/wtcr reset cause register/ watchdog peripheral control register r/w 1x x x x C 0 0 b 0481 h stcr standby control register r/w 0 0 0 1 1 1 C C b 0482 h pdrr dma controller request squelch register r/w C C C C 0 0 0 0 b 0483 h ctbr timebase timer clear register w x x x x x x x x b 0484 h gcr gear control register r/w 1 1 0 0 1 1 C 1 b 0485 h wpr watchdog reset occurrence postpone register w xxxxxxxx b 0486 h (vacancy) 0487 h 0488 h pctr pll control register r/w 0 0 C C 0 C C C b 0489 h to 0600 h (vacancy) 0601 h ddr2 port 2 data direction register w 0 0 0 0 0 0 0 0 b 0602 h to 0604 h (vacancy) 0605 h ddr6 port 6 data direction register w 0 0 0 0 0 0 0 0 b 0606 h (vacancy) 0607 h
33 mb91101/mb91101a (continued) address register name (abbreviated) register name read/write initial value 0608 h ddrb port b data direction register w 0 0 0 0 0 0 0 0 b 0609 h ddra port a data direction register w C 0 0 0 0 0 0 C b 060a h (vacancy) 060b h ddr8 port 8 data direction register w C C 0 C C 0 0 0 b 060c h asr1 area select register 1 w 00000000 b 060d h 00000001 b 060e h amr1 area mask register 1 w 00000000 b 060f h 00000000 b 0610 h asr2 area select register 2 w 00000000 b 0611 h 00000010 b 0612 h amr2 area mask register 2 w 00000000 b 0613 h 00000000 b 0614 h asr3 area select register 3 w 00000000 b 0615 h 00000011 b 0616 h amr3 area mask register 3 w 00000000 b 0617 h 00000000 b 0618 h asr4 area select register 4 w 00000000 b 0619 h 00000100 b 061a h amr4 area mask register 4 w 00000000 b 061b h 00000000 b 061c h asr5 area select register 5 w 00000000 b 061d h 00000101 b 061e h amr5 area mask register 5 w 00000000 b 061f h 00000000 b 0620 h amd0 area mode register 0 r/w C C C 0 0 1 1 1 b 0621 h amd1 area mode register 1 r/w 0 C C 0 0 0 0 0 b 0622 h amd32 area mode register 32 r/w 0 0 0 0 0 0 0 0 b 0623 h amd4 area mode register 4 r/w 0 C C 0 0 0 0 0 b 0624 h amd5 area mode register 5 r/w 0 C C 0 0 0 0 0 b 0625 h dscr dram signal control register w 00000000 b 0626 h rfcr refresh control register r/w C Cxxxxxx b 0627 h 00CCC000 b
mb91101/mb91101a 34 (continued) note: do not use (vacancy). address register name (abbreviated) register name read/write initial value 0628 h epcr0 external pin control register 0 w CCCC1100 b 0629 h C1111111 b 062a h (vacancy) 062b h epcr1 external pin control register 1 w 1 1 1 1 1 1 1 1 b 062c h dmcr4 dram control register 4 r/w 00000000 b 062d h 0000000C b 062e h dmcr5 dram control register 5 r/w 00000000 b 062f h 0000000C b 0630 h to 07fd h (vacancy) 07fe h ler little endian register w C C C C C 0 0 0 b 07ff h modr mode register w xxxxxxxx b
35 mb91101/mb91101a n interrupt causes, interrupt vectors and interrupt control register allocations (continued) interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset reset 0 00 3fc h 000ffffc h reserved for system 1 01 3f8 h 000ffff8 h reserved for system 2 02 3f4 h 000ffff4 h reserved for system 3 03 3f0 h 000ffff0 h reserved for system 4 04 3ec h 000fffec h reserved for system 5 05 3e8 h 000fffe8 h reserved for system 6 06 3e4 h 000fffe4 h reserved for system 7 07 3e0 h 000fffe0 h reserved for system 8 08 3dc h 000fffdc h reserved for system 9 09 3d8 h 000fffd8 h reserved for system 10 0a 3d4 h 000fffd4 h reserved for system 11 0b 3d0 h 000fffd0 h reserved for system 12 0c 3cc h 000fffcc h reserved for system 13 0d 3c8 h 000fffc8 h exception for undefined instruction 14 0e 3c4 h 000fffc4 h nmi request 15 0f f h fixed 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h uart0 receive complete 20 14 icr04 3ac h 000fffac h uart1 receive complete 21 15 icr05 3a8 h 000fffa8 h uart2 receive complete 22 16 icr06 3a4 h 000fffa4 h uart0 transmit complete 23 17 icr07 3a0 h 000fffa0 h uart1 transmit complete 24 18 icr08 39c h 000fff9c h uart2 transmit complete 25 19 icr09 398 h 000fff98 h dmac0 (complete, error) 26 1a icr10 394 h 000fff94 h dmac1 (complete, error) 27 1b icr11 390 h 000fff90 h dmac2 (complete, error) 28 1c icr12 38c h 000fff8c h dmac3 (complete, error) 29 1d icr13 388 h 000fff88 h dmac4 (complete, error) 30 1e icr14 384 h 000fff84 h dmac5 (complete, error) 31 1f icr15 380 h 000fff80 h
mb91101/mb91101a 36 (continued) interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset dmac6 (complete, error) 32 20 icr16 37c h 000fff7c h dmac7 (complete, error) 33 21 icr17 378 h 000fff78 h a/d converter (successive approximation conversion type) 34 22 icr18 374 h 000fff74 h 16-bit reload timer 0 35 23 icr19 370 h 000fff70 h 16-bit reload timer 1 36 24 icr20 36c h 000fff6c h 16-bit reload timer 2 37 25 icr21 368 h 000fff68 h pwm 0 38 26 icr22 364 h 000fff64 h pwm 1 39 27 icr23 360 h 000fff60 h pwm 2 40 28 icr24 35c h 000fff5c h pwm 3 41 29 icr25 358 h 000fff58 h u-timer 0 42 2a icr26 354 h 000fff54 h u-timer 1 43 2b icr27 350 h 000fff50 h u-timer 2 44 2c icr28 34c h 000fff4c h reserved for system 45 2d icr29 348 h 000fff48 h reserved for system 46 2e icr30 344 h 000fff44 h reserved for system 47 2f icr31 340 h 000fff40 h reserved for system 48 30 icr32 33c h 000fff3c h reserved for system 49 31 icr33 338 h 000fff38 h reserved for system 50 32 icr34 334 h 000fff34 h reserved for system 51 33 icr35 330 h 000fff30 h reserved for system 52 34 icr36 32c h 000fff2c h reserved for system 53 35 icr37 328 h 000fff28 h reserved for system 54 36 icr38 324 h 000fff24 h reserved for system 55 37 icr39 320 h 000fff20 h reserved for system 56 38 icr40 31c h 000fff1c h reserved for system 57 39 icr41 318 h 000fff18 h reserved for system 58 3a icr42 314 h 000fff14 h reserved for system 59 3b icr43 310 h 000fff10 h reserved for system 60 3c icr44 30c h 000fff0c h reserved for system 61 3d icr45 308 h 000fff08 h reserved for system 62 3e icr46 304 h 000fff04 h delayed interrupt cause bit 63 3f icr47 300 h 000fff00 h
37 mb91101/mb91101a (continued) * : when using in realos/fr, interrupt 0x40, 0x41 for system code. interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset reserved for system (used in realos*) 64 40 2fc h 000ffefc h reserved for system (used in realos*) 65 41 2f8 h 000ffef8 h used in int instructions 66 to 255 42 to ff 2f4 h to 000 h 000ffef4 h to 000ffc00 h
mb91101/mb91101a 38 n peripheral resources 1. i/o ports there are 2 types of i/o port register structure; port data register (pdr0 to pdrf) and data direction register (ddr0 to ddrf), where bits pdr0 to pdrf and bits ddr0 to ddrf corresponds respectively. each bit on the register corresponds to an external pin. in port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. bit 0 specifies input and 1 specifies output. ? for input (ddr = 0) setting; pdr reading operation: reads level of corresponding external pin. pdr writing operation: writes set value to pdr. ? for output (ddr = 1) setting; pdr reading operation: reads pdr value. pdr writing operation: outputs pdr value to corresponding external pin. ?block diagram pdr ddr (port data register) (data direction register) resource output enable resource output 1 0 1 0 pdr read resource input pin data bus
39 mb91101/mb91101a ( ) w C ? port data register ? data direction register bit 7 bit 0 000001 h 000005 h 00000b h 000009 h 000008 h 000012 h 000013 h xxxxxxxx b xxxxxxxx b --x--xxx b - xxxxxx - b xxxxxxxx b xxxxxxxx b xxxxxxxx b address initial value :access : readable and writable : indeterminate (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) pdr2 pdr6 pdr8 pdra pdrb pdre pdrf ( ) r/w x bit 7 bit 0 000601 h 000605 h 00060b h 000609 h 000608 h 0000d2 h 0000d3 h 00000000 b 00000000 b - - 0 - - 000 b - 000000 - b 00000000 b 00000000 b 00000000 b address initial value : access : write only : unused (w) (w) (w) (w) (w) (w) (w) ddr2 ddr6 ddr8 ddra ddrb ddre ddrf
mb91101/mb91101a 40 2. dma controller (dmac) the dma controller is a module embedded in fr family devices, and performs dma (direct memory access) transfer. dma transfer performed by the dma controller transfers data without intervention of cpu, contributing to enhanced performance of the system. ? 8 channels ? mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer ? transfer all through the area ? max. 65536 of transfer cycles ? interrupt function right after the transfer ? selectable for address transfer increase/decrease by the software ? external transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each ?block diagram sequencer edge/level detection circuit inner resource transfer request dreq0 to dreq2 dack0 to dack2 eop0 to eop2 interrupt request data buffer switcher dpdp dacsr datcr data bus mode blk dec inc / dec blk dmact sadr dadr 3 3 3 3 8 5
41 mb91101/mb91101a ? registers (dmac internal registers) ? registers (dma descriptor) bit 31 bit 0 00000200 h 00000201 h 00000202 h 00000203 h 00000204 h 00000205 h 00000206 h 00000207 h 00000208 h 00000209 h 0000020a h 0000020b h xxxxxxxx b xxxxxxxx b xxxxxxxx b x0000000 b 00000000 b 00000000 b 00000000 b 00000000 b xxxxxxxx b xxxx0000 b xxxx0000 b xxxx0000 b address initial value :access : readable and writable : indeterminate dpdp ( ) r/w x bit 16 dacsr datcr (r/w) (r/w) (r/w) bit 31 bit 0 dpdp + 0 h dpdp + 0c h dpdp + 54 h dma ch.0 descriptor dma ch.1 descriptor dma ch.7 descriptor address
mb91101/mb91101a 42 3. uart the uart is a serial i/o port for supporting asynchronous (start-stop system) communication or clk synchronous communication, and it has the following features. the mb91101 consists of 3 channels of uart. ? full double double buffer ? both a synchronous (start-stop system) communication and clk synchronous communication are available. ? supporting multi-processor mode ? perfect programmable baud rate any baud rate can be set by internal timer (refer to section 4. u-timer). ? any baud rate can be set by external clock. ? error checking function (parity, framing and overrun) ? transfer signal: nrz code ? enable dma transfer/start by interrupt.
43 mb91101/mb91101a ?block diagram control signals from external clock si (receive data) clock select circuit receive interrupt (to cpu) transmit interrupt (to cpu) receive control circuit start bit detect circuit receive bit counter receive parity counter transmit control circuit transmit start circuit transmit bit counter transmit parity counter receive status judge circuit receive shifter receive complete transmit shifter transmit start receive error generate signal for dma (to dmac) sidr sodr r-bus smr register md1 md0 cs0 scke soe scr register ssr register control signals transmit clock receive clock so (transmit data) pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sc (clock) from u-timer sc
mb91101/mb91101a 44 ? register configuration bit 15 bit 0 0000001e h 00000022 h 00000026 h 0000001f h 00000023 h 00000027 h 0000001c h 00000020 h 00000024 h 0000001d h 00000021 h 00000002 h (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) address initial value scr0 scr1 scr2 ssr0 ssr1 ssr2 smr0 smr1 smr2 sidr0/sodr0 sidr1/sidr1 sidr2/sidr2 bit 8 00000100 b 00000100 b 00000100 b 00 - - 0 - 00 b 00 - - 0 - 00 b 00 - - 0 - 00 b 00001 - 00 b 00001 - 00 b 00001 - 00 b xxxxxxxx b xxxxxxxx b xxxxxxxx b : access : readable and writable : unused : indeterminate ( ) r/w C x
45 mb91101/mb91101a 4. u-timer (16-bit timer for uart baud rate generation) the u-timer is a 16-bit timer for generating uart baud rate. combination of chip operating frequency and reload value of u-timer allows flexible setting of baud rate. the u-timer operates as an interval timer by using interrupt issued on counter underflow. the mb91101 has 3 channel u-timer embedded on the chip. an interval of up to 2 16 f can be counted. ? block diagram ? register configuration utimr (reload register) bit 15 bit 0 utim ( u-timer register) bit 15 bit 0 clock underflow to uart f (peripheral clock) control f.f. load bit 15 bit 0 00000078 h 00000079 h 0000007c h 0000007d h 00000080 h 00000081 h 0000007b h 0000007f h 00000083 h (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) address initial value 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 0 - - 00001 b 0 - - 00001 b 0 - - 00001 b utim0/utimr0 utim1/utimr1 utim2/utimr2 utimc0 utimc1 utimc2 : access : readable and writable : unused ( ) r/w C
mb91101/mb91101a 46 5. pwm timer the pwm timer can output high accurate pwm waves efficiently. mb91101 has inner 4-channel pwm timers, and has the following features. ? each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16- bit compare resister with a buffer for duty setting, and a pin controller. ? the count clock of a 16-bit down counter can be selected from the following four inner clocks. inner clock f , f /4, f /16, f /64 ? the counter value can be initialized ffff h by the resetting or the counter borrow. ? pwm output (each channel) ? resister description ? block diagram (general construction) 16-bit reload timer ch.0 16-bit reload timer ch.1 general control register 2 trg input pwm timer ch.0 trg input pwm timer ch.1 trg input pwm timer ch.2 trg input pwm timer ch.3 general control register 1 (cause selection) external trg0 to trg3 4 4 pwm0 pwm1 pwm2 pwm3
47 mb91101/mb91101a ? block diagram (for one channel) 1 / 1 1 / 4 1 / 16 1 / 64 peripheral clock prescaler ck start borrow pcsr pdut cmp load 16-bit down counter ppg mask reverse bit s r q interrupt selection irq enable soft trigger edge detect trg input pwm output
mb91101/mb91101a 48 ? register configuration bit 15 bit 0 000000dc h 000000dd h 000000df h 000000e0 h 000000e1 h 000000e2 h 000000e3 h 000000e4 h 000000e5 h 000000e6 h 000000e7 h 000000e8 h 000000e9 h 000000ea h 000000eb h 000000ec h 000000ed h 000000ee h 000000ef h 000000f0 h 000000f1 h 000000f2 h 000000f3 h 000000f4 h 000000f5 h 000000f6 h 000000f7 h 000000f8 h 000000f9 h 000000fa h 000000fb h 000000fc h 000000fd h 000000fe h 000000ff h (r/w) (r/w) (r) (w) (w) (r/w) (r/w) (r) (w) (w) (r/w) (r/w) (r) (w) (w) (r/w) (r/w) (r) (w) (w) (r/w) (r/w) address initial value bit 8 00110010 b 00010000 b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000 - b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000 - b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000 - b 00000000 b 11111111 b 11111111 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b 0000000 - b 00000000 b : access : readable and writable : read only : write only : unused : indeterminate ( ) r/w r w C x pcnh0 pcnl0 gcn2 pcnh1 pcnl1 pcnh2 pcnl2 pcnh3 pcnl3 gcn1 ptmr0 pcsr0 pdut0 ptmr1 pcsr1 pdut1 ptmr2 pcsr2 pdut2 ptmr3 pcsr3 pdut3
49 mb91101/mb91101a 6. 16-bit reload timer the 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock). the dma transfer can be started by the interruption. the mb91101 consists of 3 channels of the 16-bit reload timer. ?block diagram 16-bit reload register 16-bit down counter uf clock selector reload reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl. f C 2 f C 2 f C 2 135 3 internal clock prescaler clear exck gate 2 retrigger irq pwm (ch.0, ch.1) a/d (ch.2) r-bus
mb91101/mb91101a 50 ? register configuration bit 15 bit 0 0000002e h 0000002f h 00000036 h 00000037 h 00000042 h 00000043 h 0000002a h 0000002b h 00000032 h 00000033 h 0000003e h 0000003f h 00000028 h 00000029 h 00000030 h 00000031 h 0000003c h 0000003d h ----0000 b 00000000 b ---- 0000 b 00000000 b ----0000 b 00000000 b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b address initial value :access : readable and writable : read only : write only : unused : indeterminate (r/w) (r/w) (r/w) (r) (r) (r) (w) (w) (w) tmcsr0 tmcsr1 tmcsr2 tmr0 tmr1 tmr2 tmrlr0 tmrlr1 tmrlr2 ( ) r/w r w C x
51 mb91101/mb91101a 7. bit search module the bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. ?block diagram ? register configuration input latch single-detection data recovery bit search circuit search result address decoder detection mode d-bus 000003f0 h 000003f1 h 000003f2 h 000003f3 h 000003f4 h 000003f5 h 000003f6 h 000003f7 h 000003f8 h 000003f9 h 000003fa h 000003fb h 000003fc h 000003fe h 000003fd h 000003ff h bit 31 bit 0 xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b xxxxxxxx b address initial value (w) (w) (w) (w) bit 16 : access : readable and writable : read only : write only : indeterminate ( ) r/w r w x bsd0 bsd1 bsdc bsrr
mb91101/mb91101a 52 8. 10-bit a/d converter (successive approximation conversion type) the a/d converter is the module which converts an analog input voltage to a digital value, and it has following features. ? minimum converting time: 5.6 m s/ch. (system clock: 25 mhz) ? inner sample and hold circuit ? resolution: 10 bits ? analog input can be selected from 4 channels by program. single convert mode: 1 channel is selected and converted. scan convert mode: converting continuous channels. maximum 4 channels are programmable. continuous convert mode: converting the specified channel repeatedly. stop convert mode: after converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. ? dma transfer operation is available by interruption. ? operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer (rising edge). ?block diagram successive approximation register internal voltage generator av cc avr av ss mpx comparator an0 an1 an2 an3 sample & hold circuit data register (adcr) a/d control register (adcs) prescaler operating clock atg trigger start tim0 (internal connection) (16-bit reload timer ch.2) timer start f (peripheral clock) r-bus input circuit decoder
53 mb91101/mb91101a ? register configuration bit 15 bit 0 0000003a h 0000003b h 00000038 h 00000039 h 00000000 b 00000000 b ------xx b xxxxxxxx b address initial value adcs adcr (r/w) (r) : access : readable and writable : read only : unused : indeterminate ( ) r/w r C x
mb91101/mb91101a 54 9. interrupt controller the interrupt controller processes interrupt acknowledgments and arbitration between interrupts. ?block diagram r-bus level0* 4 im int0* 2 or priority judgment nmi nmi processing ri00 ri47 (dlyirq) dlyi* 1 level judgment icr00 icr47 vector judgment 4 5 5 6 6 level vector generation hldreq cancel request level4 to hldcan* 3 vct0* 5 vct5 to *1: dlyi stands for delayed interrupt module (delayed interrupt generation block) (refer to the section 11. delayed interrupt module for detail). *2: int0 is a wake-up signal to clock control block in the sleep or stop status. *3: hldcan is a bus release request signal for bus masters other than cpu. *4: level5 to level0 are interrupt level outputs. *5: vct5 to vct0 are interrupt vector outputs.
55 mb91101/mb91101a ? register configuration icr00 icr01 icr02 icr03 icr04 icr05 icr06 icr07 icr08 icr09 icr10 icr11 icr12 icr13 icr14 icr15 icr16 bit 7 bit 0 00000400 h 00000401 h 00000402 h 00000403 h 00000404 h 00000405 h 00000406 h 00000407 h 00000408 h 00000409 h 0000040a h 0000040b h 0000040c h 0000040d h 0000040e h 0000040f h 00000410 h - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) address initial value icr17 icr18 icr19 icr20 icr21 icr22 icr23 icr24 icr25 icr26 icr27 icr28 icr29 icr30 icr31 icr47 hrcl dicr bit 7 bit 0 00000411 h 00000412 h 00000413 h 00000414 h 00000415 h 00000416 h 00000417 h 00000418 h 00000419 h 0000041a h 0000041b h 0000041c h 0000041d h 0000041e h 0000041f h 0000042f h 00000431 h 00000430 h - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - 11111 b (r/w) - - - - - - - 0 b (r/w) address initial value :access : redable and writable : unused ( ) r/w C
mb91101/mb91101a 56 10. external interrupt/nmi control block the external interrupt/nmi control block controls external interrupt request signals input to nmi pin and int0 to int3 pins. detecting levels can be selected from h, l, rising edge and falling edge (not for nmi pin). ?block diagram ? register configuration interrupt enable register interrupt cause register request level setting register gate cause f/f edge detection circuit interrupt request 8 8 8 9 5 int0 to int3 nmi r-bus bit 15 bit 0 00000000 b 00000000 b 00000000 b address initial value enir elvr (r/w) (r/w) (r/w) bit 8 eirr 00000095 h 00000094 h 00000099 h : access : redable and writable ( ) r/w
57 mb91101/mb91101a 11. delayed interrupt module delayed interrupt module is a module which generates a interrupt for changing a task. by using this delayed interrupt module, an interrupt request to cpu can be generated/cancelled by the software. refer to the section 9. interrupt controller for delayed interrupt module block diagram. ? register configuration bit 7 bit 0 -------0 b address initial value dicr (r/w) 00000430 h :access : redable and writable :unused ( ) r/w C
mb91101/mb91101a 58 12. clock generation (low-power consumption mechanism) the clock control block is a module which undertakes the following functions. ? cpu clock generation (including gear function) ? peripheral clock generation (including gear function) ? reset generation and cause hold ? standby function (including hardware standby) ? dma request prohibit ? pll (multiplier circuit) embedded ?block diagram gear control register (gcr) [gear control block] pctr register cpu gear peripheral gear oscillator circuit x0 x1 1/2 pll internal clock generation circuit cpu clock internal bus clock external bus clock peripheral dma clock internal peripheral clock [stop/sleep control block] internal interrupt request internal reset standby control register (stcr) stop state sleep state cpu hold request internal reset reset generation f/f cpu hold enable hst pin dma request power on sel rst pin dma request prohibit register (pdrr) [dma prohibit circuit] reset cause register (rsrr) timebase timer count clock watchdog reset postpone register [watchdog control block] timebase timer clear register (ctbr) watchdog reset generation postpone register (wpr) r-bus selection circuit [reset cause circuit] status transition control circuit
59 mb91101/mb91101a ? register configuration bit 15 bit 0 1xxxx - 0 0 b 000111 - - b ----0000 b xxxxxxxx b 110011 - 1 b xxxxxxxx b 00--0--- b address initial value bit 8 00000480 h 00000481 h 00000482 h 00000483 h 00000484 h 00000485 h 00000488 h stcr ctbr wpr rsrr/wtcr pdrr gcr pctr (r/w) (r/w) (r/w) (w) (r/w) (w) (r/w) : access : redable and writable : write only : unused : indeterminate ( ) r/w w C x
mb91101/mb91101a 60 13. external bus interface the external bus interface controls the interface between the device and the external memory and also the external i/o, and has the following features. ? 25-bit (32 mbytes) address output ? 6 independent banks owing to the chip select function. can be set to anywhere on the logical address space for minimum unit 64 kbytes. total 32 mbytes 6 area setting is available by the address pin and the chip select pin. ? 8/16-bit bus width setting are available for every chip select area. ? programmable automatic memory wait (max. for 7 cycles) can be inserted. ? dram interface support three kinds of dram interface: double cas dram (normally dram i/f) single cas dram hyper dram 2 banks independent control (ras, cas, etc. control signals) dram select is available from 2cas/1we and 1cas/2we. hi-speed page mode supported cbr/self refresh supported programmable wave form ? unused address/data pin can be used for i/o port. ? little endian mode supported ? clock doubler: internal bus 50 mhz, external bus 25 mhz
61 mb91101/mb91101a ?block diagram address bus data bus a-out external data bus write buffer read buffer switch mux switch +1 or +2 inpage dmcr dram control refresh counter asr amr data block address block address buffer shifter comparator external address bus cs0 to cs5 ras0, ras1 cs0l, cs1l cs0h, cs1h dw0, dw1 underflow to tbt external pin control block registers and control rd wr0, wr1 brq bgrnt clk rdy all blocks control 32 6 8 3 4 32
mb91101/mb91101a 62 ? register configuration bit 31 bit 0 (w) (w) (w) (w) (w) (w) (w) (w) (w) (w) address initial value bit 16 00000000 b 00000001 b 00000000 b 00000000 b 00000000 b 00000010 b 00000000 b 00000000 b 00000000 b 00000011 b 00000000 b 00000000 b 00000000 b 00000100 b 00000000 b 00000000 b 00000000 b 00000101 b 00000000 b 00000000 b :access : redable and writable : write only :unused : indeterminate ( ) r/w w C x asr1 amr1 asr2 amr2 asr3 amr3 asr4 amr4 asr5 amr5 amd0 amd1 amd32 amd4 amd5 dscr rfcr epcr0 dmcr4 dmcr5 ler modr - - xxxxxx b 00 - - - 000 b - - - - 1100 b - 1111111 b 11111111 b 00000000 b 0000000 - b 00000000 b 0000000 - b -----000 b xxxxxxxx b - - - 00111 b 0 - - 00000 b 00000000 b 0 - - 00000 b 0 - - 00000 b 00000000 b (r/w) (r/w) (r/w) (r/w) (r/w) (w) (r/w) (w) (w) (r/w) (r/w) (w) (w) 0000060c h 0000060d h 0000060e h 0000060f h 00000610 h 00000611 h 00000612 h 00000613 h 00000614 h 00000615 h 00000616 h 00000617 h 00000618 h 00000619 h 0000061a h 0000061b h 0000061c h 0000061d h 0000061e h 0000061f h 00000626 h 00000627 h 00000628 h 00000629 h 0000062b h 0000062c h 0000062d h 0000062e h 0000062f h 000007fe h 000007ff h 00000620 h 00000621 h 00000622 h 00000623 h 00000624 h 00000625 h epcr1
63 mb91101/mb91101a n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: v cc 5 must not be less than v ss C 0.3 v. *2: make sure that the voltage does not exceed v cc 5 + 0.3 v, such as when turning on the device. *3: maximum output current is a peak current value measured at a corresponding pin. *4: average output current is an average current for a 100 ms period at a corresponding pin. *5: average total output current is an average current for a 100 ms period for all corresponding pins. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage at 5 v power supply v cc 5v ss C 0.3 v ss + 6.5 v v cc 3 v at 3 v power supply v cc 5v cc 3 C 0.3 v ss + 6.5 v *1 v cc 3v ss C 0.3 v ss + 3.6 v *1 analog supply voltage av cc v ss C 0.3 v ss + 3.6 v *2 analog reference voltage avrh v ss C 0.3 v ss + 3.6 v *2 analog pin input voltage v ia v ss C 0.3 av cc + 0.3 v input voltage v i v ss C 0.3 v cc 5 + 0.3 v output voltage v o v ss C 0.3 v cc 5 + 0.3 v l level maximum output current i ol 10ma*3 l level average output current i olav 4ma*4 l level maximum total output current s i ol 100 ma l level average total output current s i olav 50ma*5 h level maximum output current i oh C10 ma *3 h level average output current i ohav C4ma*4 h level maximum total output current s i oh C50 ma h level average total output current s i ohav C20 ma *5 power consumption p d 500 mw operating temperature t a 0+70 c storage temperature tstg C55 +150 c
mb91101/mb91101a 64 2. recommended operating conditions (1) at 5 v operation (4.5 v to 5.5 v) (v ss = av ss = 0.0 v) *1: at v cc 5, the ram state holding is not warranted in stop mode. *2: v cc 3 is used for the bypass capacitor pin. *3: use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic capacitor. and select the larger capacity smoothing condenser to connect to the power supply (v cc 5) than c s . (2) at 3 v operation (2.7 v to 3.6 v) (v ss = av ss = 0.0 v) * : connect to v cc 5 for the power supply pin. parameter symbol value unit remarks min. max. power supply voltage v cc 5 4.5 5.5 v normal operation v cc 5*1 *1v retaining the ram state in stop mode v cc 3 v*2 analog supply voltage av cc v ss + 2.7 v cc + 3.6 v analog reference voltage avrh v ss C 0.3 av cc v operating temperature t a 0+70 c smoothing capacitor c s 0.1 1.0 m fv cc 3 pin *2 parameter symbol value unit remarks min. max. power supply voltage v cc 5 2.7 3.6 v normal operation v cc 52.73.6v retaining the ram state in stop mode v cc 32.73.6v* analog power supply voltage av cc v ss + 2.7 v cc + 3.6 v analog reference voltage avrh av ss av cc v operating temperature t a 0+70 c v cc 5 av cc avrh av ss v ss v cc 3 5 v gnd using with 5 v power supply v cc 5 av cc avrh av ss v ss v cc 3 3 v 3 v gnd using with 3 v power supply about 0.1 m f ? connecting to a power supply
65 mb91101/mb91101a warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. 5.5 4.5 04050 25 f cp /f cpp (mhz) 50 12.5 20 25 40 0 0 10 25 50 f c (mhz) internal clock supply voltage max. internal clock frequency setting 0.625 3.6 3.3 3.0 2.7 normal operation warranty range (t a = 0 c to +70 c) net masked area are f cpp . v cc (v) 12.5 pll system (4 multiplication) f cp /f cpp (mhz) 5 source oscillating input clock external clock self-oscillation notes: when using pll, the external clock must be used between 10.0 mhz to 12.5 mhz. pll oscillation stabilizing period > 100 m s the setting of internal clock must be within above ranges. 3.0 v 0.3 v 3.3 v 0.3 v power supply at 5 v power supply at 3 v divide-by-2 system cpu peripheral f cp f cpp
mb91101/mb91101a 66 3. dc characteristics (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) * : v cc 3 = 3.3 0.2 v (internal regulator output voltage) when using 5 v power supply, v cc 3 = power supply voltage when using 3 v power supply (internal regulator unused) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih input pin except for hysteresis input 0.65 v cc 3 v cc 5 + 0.3 v* v ihs hst , nmi , rst , pa 1 t o pa 6 , pb0 to pb7, pe0 to pe7, pf0 to pf7 0.8 v cc 3 v cc 5 + 0.3 v hysteresis input * l level input voltage v il input other than following symbols v ss C 0.3 0.25 v cc 3 v* v ils hst , nmi , rst , pa 1 t o pa 6 , pb0 to pb7, pe0 to pe7, pf0 to pf7 v ss C 0.3 0.2 v cc 3 v hysteresis input * h level output voltage v oh d16 to d31, a00 to a24, p6 to pf v cc 5 = 4.5 v i oh = C4.0 ma v cc C 0.5 v l level output voltage v ol d16 to d31, a00 to a24, p6 to pf v cc 5 = 4.5 v i ol = 4.0 ma 0.4v input leakage current (hi-z output leakage current) i li d00 to d31, a00 to a23, p8 to pf v cc 5 = 5.5 v 0.45 v < v i < v cc C5 +5 m a pull-up resistance r pull rst v cc 5 = 5.5 v v i = 0.45 v 25 50 100 k w power supply current i cc v cc f c = 12.5 mhz v cc 5 = 5.5 v 75100ma (4 multiplication) operation at 50 mhz i ccs v cc f c = 12.5 mhz v cc 5 = 5.5 v 40 60 ma sleep mode i cch v cc t a = +25 c v cc 5 = 5.5 v 10100 m a stop mode input capacitance c in except for v cc 5, v cc 3, av cc , av ss , v ss 10pf
67 mb91101/mb91101a 4. ac characteristics measurement conditions ?v cc = 5.0 v 10% ?v cc = 2.7 v to 3.6 v ? load conditions parameter symbol value unit remarks min. typ. max. h level input voltage v ih 2.4v l level input voltage v il 0.8v h level output voltage v oh 2.4v l level output voltage v ol 0.8v parameter symbol value unit remarks min. typ. max. h level input voltage v ih 1/2 v cc v l level input voltage v il 1/2 v cc v h level output voltage v oh 1/2 v cc v l level output voltage v ol 1/2 v cc v v oh v ol v ih v il v cc 0.0 v input output v oh v ol v ih v il v cc 0.0 v input output c = 50 pf output pin (v cc = 5.0v 10%)
mb91101/mb91101a 68 ? load capacitance - delay characteristics (output delay with reference to the internal) 35 30 25 20 15 10 5 0 0 20 40 50 60 80 100 120 c (pf) 5 v fall 3 v rise 5 v rise 3 v fall (ns)
69 mb91101/mb91101a (1) clock timing rating (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) *1: frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. *2: these values are for a minimum clock of 10 mhz input to x0, a divide-by-2 system of the source oscillation and a 1/8 gear. *3: values when using the doubler and cpu operation at 50 mhz. parameter symbol pin name condition value unit remarks min. max. clock frequency f c x0, x1 when using pll 10 12.5 mhz f c x0, x1 self-oscillation (divide-by-2 input) 10 25 mhz f c x0, x1 external clock (divide-by-2 input) 10 25 mhz clock cycle time t c x0, x1 when using pll 80 100 ns t c x0, x1 40 100 ns frequency shift ratio (when locked) d f when using pll 5 % *1 input clock pulse width p wh , p wl x0, x1 25 ns input to x0 only, when using 5 v power supply p wh , p wl x0, x1 10 ns input to x0, x1 input clock rising/falling time t cr , t cf x0, x1 8 ns (t cr + t cf ) internal operating clock frequency f cp cpu system 0.625* 2 50 mhz f cpb bus system 0.625* 2 25* 3 mhz f cpp peripheral system 0.625* 2 25 mhz internal operating clock cycle time t cp cpu system 20 1600* 2 ns t cpb bus system 40* 3 1600* 2 ns t cpp peripheral system 40 1600* 2 ns d f = 100 (%) | a | f 0 center frequency f 0 + a a +
mb91101/mb91101a 70 0.8 v cc 0.2 v cc t cf t cr t c p wl p wh ? clock timing rating measurement conditions
71 mb91101/mb91101a (2) clock output timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cp , t cpb (internal operating clock cycle time): refer to (1) clock timing rating. *1: t cyc is a frequency for 1 clock cycle including a gear cycle. use the doubler when cpu frequency is above 25 mhz. *2: rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. min. : (1 C n/2) t cyc C 10 max. : (1 C n/2) t cyc + 10 select a gear cycle of 1 when using the doubler. *3: rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. min. : n/2 t cyc C 10 max. : n/2 t cyc + 10 select a gear cycle of 1 when using the doubler. parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk t cp ns*1 t cyc clk using the doubler t cpb ns clk - ? clk t chcl clk 1/2 t cyc C 10 1/2 t cyc + 10 ns *2 clk ? clk - t clch clk 1/2 t cyc C 10 1/2 t cyc + 10 ns *3 clk v oh v ol v oh t cyc t chcl t clch
mb91101/mb91101a 72 the relation between source oscillation input and clk pin for configured by chc/cck1/cck0 settings of gcr (gear control register) is as follows: however, in this chart source oscillation input means x0 input clock. cck1/0: 00 source oscillation input (when using the doublure) source oscillation input (1) pll system (chc bit of gcr set to 0) (2) 2 dividing system (chc bit of gcr set to 1) (a) gear 1 clk pin cck1/0: 00 (b) gear 1/2 clk pin cck1/0: 01 (c) gear 1/4 clk pin cck1/0: 10 (d) gear 1/8 clk pin cck1/0: 11 t cyc t cyc t cyc t cyc t cyc (a) gear 1 clk pin
73 mb91101/mb91101a ? discreet type ( ): c 1 and c 2 internally connected 3 contacts type. oscillation frequency [mhz] model load capacitance c 1 = c 2 [pf] power supply voltage v cc 5 [v] 5.00 to 6.30 csa mg 30 2.9 to 5.5 cst mgw (30) csa mg093 30 2.7 to 5.5 cst mgw093 (30) 6.31 to 10.0 csa mtz 30 2.9 to 5.5 cst mtw (30) csa mtz093 30 2.7 to 5.5 cst mtw093 (30) 10.1 to 13.0 csa mtz 30 3.0 to 5.5 cst mtw (30) csa mtz093 30 2.9 to 5.5 cst mtw093 (30) 13.01 to 15.00 csa mxz040 15 3.2 to 5.5 cst mxw0c3 (15) c 2 c 1 * recommended circuit (2 contacts) x0 x1 recommended circuit (3 contacts) x0 x1 * c 1 c 2 c 1 , c 2 internally connected. * : murata mfg. co., ltd. ? ceramic oscillator applications
mb91101/mb91101a 74 (3) reset/hardware standby input ratings (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cp (internal operating clock cycle time): refer to (1) clock timing rating. parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst t cp 5ns hardware standby input time t hstl hst t cp 5ns rst hst 0.2 v cc 0.2 v cc t rstl , t hstl
75 mb91101/mb91101a (4) power on supply specifications (power-on reset) (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t c (clock cycle time): refer to (1) clock timing rating. * : v cc < 0.2 v before the power supply rising parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc v cc = 5.0 v 50 m s* t r v cc 30ms* t r v cc v cc = 3.0/ 3.3 v 50 m s* t r v cc 18ms* power supply shut off time t off v cc 1ms repeated operations oscillation stabilizing time t osc 2 t c 2 21 + 100 m s ns 0.2 v t r 0.9 v cc v cc v ss a voltage rising rate of 50 mv/ms or less is recommended. v cc sudden change in supply voltage during operation may initiate a power-on sequence. to change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. note: t rstl : reset input time t off v cc rst (oscillation stabilizing time) note: set rst pin to l level when turning on the device, at least the described above duration after the supply voltage reaches vcc is necessary before turning the rst to h level. t osc t rstl + (t c 2 19 ) 42 ms approx. 336 ms approx. (@12.5 mhz) stabilizing time * *: reset cant be done during regulator stabilizing time. regulator
mb91101/mb91101a 76 (5) normal bus access read/write operation (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. *1: when bus timing is delayed by automatic wait insertion or rdy input, add (t cyc extended cycle number for delay) to this rating. *2: rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation: (2 C n/2) t cyc C 25 parameter symbol pin name condition value unit remarks min. max. cs0 to cs5 delay time t chcsl clk, cs0 to cs5 15ns t chcsh clk, cs0 to cs5 15ns address delay time t chav clk, a24 to a00 15ns data delay time t chdv clk, d31 to d16 15ns rd delay time t clrl clk, rd 6ns t clrh clk, rd 6ns wr0 , wr1 delay time t clwl clk, wr0 , wr1 6ns t clwh clk, wr0 , wr1 6ns valid address ? valid data input time t avdv a24 to a00, d31 to d16 3/2 t cyc C 25 ns *1 *2 rd ? valid data input time t rldv rd , d31 to d16 t cyc C 10 ns *1 data set up ? rd - time t dsrh rd , d31 to d16 10 ns rd -? data hold time t rhdx rd , d31 to d16 0ns
77 mb91101/mb91101a v oh clk v ol v oh v ol ba2 v oh t chcsl t chav v ol v oh v ol t clrl v ol t clwl v ol t chdv v ol v oh write v ol v oh t clrh v oh v ih v il v ih v il t dsrh t rhdx t clwh v oh read v oh v ol t chcsh v oh cs0 to cs5 a24 to a00 rd d31 to d16 wr0, wr1 d31 to d16 ba1 t cyc t rldv t avdv
mb91101/mb91101a 78 (6) ready input timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) parameter symbol pin name condition value unit remarks min. max. rdy set up time ? clk t rdys rdy, clk 15 ns clk ? rdy hold time t rdyh rdy, clk 0 ns clk v oh v oh v ol v ol v il v ih v ih v il t rdyh t rdyh rdy when wait(s) is inserted. rdy when no wait is inserted. v ih v il v il v ih t cyc t rdys t rdys
79 mb91101/mb91101a (7) hold timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. note: there is a delay time of more than 1 cycle from brq input to bgrnt change. parameter symbol pin name condition value unit remarks min. max. bgrnt delay time t chbgl clk, bgrnt 6ns t chbgh clk, bgrnt 6ns pin floating ? bgrnt time t xhal bgrnt t cyc C 10 t cyc + 10 ns bgrnt -? pin valid time t hahv bgrnt t cyc C 10 t cyc + 10 ns clk v oh t chbgl v ol each pin high impedance v oh v oh v oh v oh v ol v oh v ol v oh t chbgh brq bgrnt t cyc t xhal t hahv
mb91101/mb91101a 80 (8) normal dram mode read/write cycle (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. cas: cs0l to cs1h pins are for cas signal outputs. dw : dw0 , dw1 and cs0h to cs1h are used for we outputs. *1: when q1 cycle or q4 cycle is extended for 1 cycle, add t cyc time to this rating. *2: rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation: (3 C n/2) t cyc C 16 parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk, ras 6ns t chral clk, ras 6 ns cas delay time t clcasl clk, cas 6 ns t clcash clk, cas 6 ns row address delay time t chrav clk, a24 to a00 15ns column address delay time t chcav clk, a24 to a00 15ns dw delay time t chdwl clk, dw 15ns t chdwh clk, dw 15ns output data delay time t chdv1 clk, d31 to d16 15ns ras ? valid data input time t rldv ras, d31 to d16 5/2 t cyc C 16 ns *1 *2 cas ? valid data input time t cldv cas, d31 to d16 t cyc C 17 ns *1 cas -? data hold time t cadh cas, d31 to d16 0ns
81 mb91101/mb91101a v ol v oh write v ol v oh d31 to d16 v ol v oh column address v ol v oh v ol v oh v ol v oh clk v ol q2 q1 q3 q4 q5 v oh v oh v oh v oh v oh v ol v ol v ol v oh t clrah t chral v ol t clcash v oh t clcash t chcav row address t chrav read v il v ih v il v ih t cadh v ol v oh t chdwl t chdwh t chdv1 d31 to d16 ras cas a24 to a00 dw t cyc t rldv t cldv
mb91101/mb91101a 82 (9) normal dram mode fast page read/write cycle (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. cas: cs0l to cs1h pins are for cas signal outputs. dw : dw0 , dw1 and cs0h to cs1h are used for we outputs. * : when q4 cycle is extended for 1 cycle, add t cyc time to this rating. parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk, ras 6ns cas delay time t clcasl clk, cas 6 ns t clcash clk, cas 6 ns column address delay time t chcav clk, a24 to a00 15ns dw delay time t chdwh clk, dw 15ns output data delay time t chdv1 clk, d31 to d16 15ns cas ? valid data input time t cldv cas, d31 to d16 t cyc C 17 ns * cas -? data hold time t cadh cas, d31 to d16 0ns
83 mb91101/mb91101a v ol v oh v ol v oh column address v ol v oh v il v ih v il v ih t clcash t chcav column address column address v ol v oh v ol v oh v oh v ol v oh v ol v oh t chdwh t chdv1 write read read v il v ih read d31 to d16 clk d31 to d16 ras cas a24 to a00 dw q4 q5 v oh v ol q5 v ol q4 q5 v oh v ol t clrah v oh v oh v ol t clcasl v il v ih v il v ih v il v ih t cadh write t cldv
mb91101/mb91101a 84 (10) single dram timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah2 clk, ras 6ns t chral2 clk, ras 6 ns cas delay time t chcasl2 clk, cas n/2 t cyc ns t chcash2 clk, cas 6 ns row address delay time t chrav2 clk, a24 to a00 15ns column address delay time t chcav2 clk, a24 to a00 15ns dw delay time t chdwl2 clk, dw 15ns t chdwh2 clk, dw 15ns output data delay time t chdv2 clk, d31 to d16 15ns cas ? valid data input time t cldv2 cas, d31 to d16 (1 C n/2) t cyc C 17 ns cas -? data hold time t cadh2 clk, d31 to d16 0ns
85 mb91101/mb91101a q1 q2 q3 q4s q4s q4s v oh t cyc t chcasl2 t chcash2 t clrah2 t chral2 t chrav2 t chdwl2 t chdwh2 t chdv2 t chdv2 t cadh2 t cldv2 t chcav2 v oh row address clk ras cas dw a24 to a00 d31 to d16 d31 to d16 column-0 column-1 column-2 read-0 read-1 read-2 write-0 write-2 write-1 v ol v ol *1 *2 v oh v oh v oh v oh v oh v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v ol v ol v oh v ol v oh v ol v oh v ol v ih v il v ih v il v oh *1: q4s indicates q4sr (read) of single dram cycle or q4sw (write) cycle. *2: indicates the timing when the bus cycle begins from the high spead page mode.
mb91101/mb91101a 86 (11) hyper dram timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah3 clk, ras 6ns t chral3 clk, ras 6 ns cas delay time t chcasl3 clk, cas n/2 t cyc ns t chcash3 clk, cas 6 ns row address delay time t chrav3 clk, a24 to a00 15ns column address delay time t chcav3 clk, a24 to a00 15ns rd delay time t chrl3 clk, rd 15ns t chrh3 clk, rd 15ns t clrl3 clk, rd 15ns dw delay time t chdwl3 clk, dw 15ns t chdwh3 clk, dw 15ns output data delay time t chdv3 clk, d31 to d16 15ns cas ? valid data input time t cldv3 cas, d31 to d16 t cyc C 17 ns cas ? data hold time t cadh3 clk, d31 to d16 0ns
87 mb91101/mb91101a q1 q2 q3 q4h q4h q4h v oh t cyc t chcasl3 t chcash3 t clrah3 t chral3 t chrav3 t chcav3 v oh row address clk ras cas dw rd a24 to a00 d31 to d16 d31 to d16 column-0 column-1 column-2 v ol v ol v ol *1 v oh v oh v oh v oh v ol v ol v ol v oh v ol v oh v ol v oh v ol t chdwl3 t chdwh3 t chdv3 t chrl3 t chrh3 t cadh3 t cldv3 read-0 read-1 t clrl3 t chdv3 write-0 write-2 write-1 *2 *2 v oh v oh v ol v ol v ol v ih v il v ih v il v oh v oh v ol v oh v ol v oh v ol v oh v ol v ol v oh *1: q4h indicates q4hr (read) of single dram cycle or q4hw (write) cycle. *2: indicates the timing when the bus cycle begins from the high spead page mode.
mb91101/mb91101a 88 (12) cbr refresh (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) cas: cs0l to cs1h pins are for cas signal outputs. parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk, ras 6ns t chral clk, ras 6 ns cas delay time t clcasl clk, cas 6 ns t clcash clk, cas 6 ns t clcash clk ras cas v ol v ol r4 v oh v ol t clrah r3 r2 r1 v ol v oh v oh v oh v oh v ol t chral t clcasl dw t cyc
89 mb91101/mb91101a (13) self refresh (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) cas: cs0l to cs1h pins are for cas signal outputs. parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk, ras 6ns t chral clk, ras 6 ns cas delay time t clcasl clk, cas 6 ns t clcash clk, cas 6 ns clk ras cas v ol t chral v oh t clcasl t clrah v oh sr2 v oh sr3 v ol v ol sr3 v ol v oh v oh t clcash t cyc sr1
mb91101/mb91101a 90 (14) uart timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cycp : a cycle time of peripheral system clock notes: this rating is for ac characteristics in clk synchronous mode. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc internal shift clock mode 8 t cycp ns sclk ? sclk - t sclch 4 t cycp C10 4 t cycp +10 ns sclk -? sclk t schcl 4 t cycp C10 4 t cycp +10 ns sclk ? sout delay time t slov C80 80 ns valid sin ? sclk - t ivsh 100 ns sclk -? valid sin hold time t shix 60ns serial clock h pulse width t shsl external shift clock mode 4 t cycp ns serial clock l pulse width t slsh 4 t cycp ns sclk ? sout delay time t slov 150ns valid sin ? sclk - t ivsh 60ns sclk -? valid sin hold time t shix 60ns sclk sout sin sclk sout sin t scyc t sclch t schcl t slov t ivsh t shix t shsl t slsh t slov t ivsh t shix v ol v ol v oh v il v il v ih v ih v ol v oh v il v ih v ol v oh v il v ih v il v ih v il v ih ? internal shift clock mode ? external shift clock mode
91 mb91101/mb91101a (15) trigger system input timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cycp : a cycle time of peripheral system clock parameter symbol pin name condition value unit remarks min. max. a/d start trigger input time t trgh , t trgl at g 5 t cycp ns pwm external trigger input time t trgh , t trgl trg0 to trg3 5 t cycp ns atg trg0 to trg3 t trgh t trgl v il v il v ih v ih
mb91101/mb91101a 92 (16) dma controller timing (v cc 5 = 5.0 v 10%, v ss = av ss = 0.0 v, t a = 0 c to +70 c) (v cc 5 = v cc 3 = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to +70 c) t cyc (a cycle time of peripheral system clock): refer to (2) clock output timing. parameter symbol pin name condition value unit remarks min. max. dreq input pulse width t drwh dreq0 to dreq2 2 t cyc ns dack delay time (normal bus) (normal dram) t cldl clk, dack0 to dack2 6ns t cldh clk, dack0 to dack2 6ns eop delay time (normal bus) (normal dram) t clel clk, eop0 to eop2 6ns t cleh clk, eop0 to eop2 6ns dack delay time (single dram) (hyper dram) t chdl clk, dack0 to dack2 n/2 t cyc ns t chdh clk, dack0 to dack2 6ns eop delay time (single dram) (hyper dram) t chel clk, eop0 to eop2 n/2 t cyc ns t cheh clk, eop0 to eop2 6ns clk dreq0 to dreq2 v oh v oh v ih v ih v ol v ol v ol v ol v oh v oh dack0 to dack2 eop0 to eop2 (normal bus) (normal dram) dack0 to dack2 eop0 to eop2 (single dram) (hyper dram) t cyc t drwh t cldl t clel t chdl t chel t cldh t cleh t chdh
93 mb91101/mb91101a 5. a/d converter block electrical characteristics (av cc = 2.7 v to 3.6 v, av ss = 0.0 v, avrh = 2.7 v, t a = 0 c to +70 c) *1: av cc = 2.7 v C 3.6 v *2: current value for a/d converters not in operation, cpu stop mode (v cc = av cc = avrh = 3.6 v) notes: ? as the absolute value of avrh decreases, relative error increases. ? output impedance of external circuit of analog input under following conditions; output impedance of external circuit < 10 k w . if output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling (sampling time is 5.6 m s for a machine clock of 25 mhz). parameter symbol pin name value unit min. typ. max. resolution 10 10 bit total error 4.0 lsb linearity error 3.5 lsb differentiation linearity error 2.0 lsb zero transition voltage v ot an0 to an3 C1.5 +0.5 +2.5 lsb full-scale transition voltage v fst an0 to an3 avrh C 4.5 avrh C 1.5 avrh + 0.5 lsb conversion time 5.6 * 1 m s analog port input current i ain an0 to an3 0.1 10 m a analog input voltage v ain an0 to an3 av ss avrh v reference voltage avrh av ss av cc v power supply current i a av cc 4ma i ah av cc 5 * 2 m a reference voltage supply current i r avrh 200 m a i rh avrh 5 * 2 m a conversion variance between channels an0 to an3 4 lsb r on1 r on1 : 0.2 k w r on2 : 1.4 k w r on3 : 1.4 k w r on4 : 0.2 k w c 0 : 16.6 pf c 1 : 4.0 pf r on2 r on3 r on4 c 0 c 1 analog input note: listed values are for reference purposes only. comparator sample and hold circuit ? analog input circuit model plan
mb91101/mb91101a 94 6. a/d converter glossary ? resolution the smallest change in analog voltage detected by a/d converter. ? linearity error a deviation of actual conversion characteristic from a line connecting the zero-traction point (between 00 0000 0000 ? 00 0000 0001) to the full-scale transition point (between 11 1111 1110 ? 11 1111 1111). ? differential linearity error a deviation of a step voltage for changing the lsb of output code from ideal input voltage. (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh linearity error analog input actual conversion characteristic {1 lsb (n C 1) + v ot } v nt actual conversion characteristic ideal characteristic 1 lsb = [v] v fst C v ot 1022 linearity error of digital output n = v nt C {1 lsb (n C 1) + v ot } 1 lsb v ot : a voltage for causing transition of digital output from (000) h to (001) h (measured value) v fst (measured value) v ot (measured value) nC1 avrl avrh differential linearity error analog input nC2 n n+1 actual characteristic ideal characteristic actual conversion characteristic v nt (measured value) v (n + 1)t (measured value) [lsb] differential linearity error of digital output n = v (n + 1)t C v nt 1 lsb [lsb] C 1 v fst : a voltage for causing transition of digital output from (3fe) h to (3ff) h v nt : a voltage for causing transition of digital output from (n C 1) h to n digital output digital output
95 mb91101/mb91101a (continued) ? total error a difference between actual value and theoretical value. the overall error includes zero-transition error, full- scale transition error and linearity error. v nt : a voltage for causing transition of digital output from (n C 1) to n 3ff 3fe 3fd 004 003 002 001 avrl avrh total error analog input actual conversion characteristic 1.5 lsb {1 lsb (n C 1) + 0.5 lsb} v nt (measured value) actual conversion characteristic ideal characteristic 0.5 lsb (ideal value) = avrl + 0.5 lsb [lsb] v ot (ideal value) = avrl C 1.5 lsb [v] [v] v fst total error of digital output n = v nt C {1 lsb (n C 1) + 0.5 lsb} 1 lsb' digital output 1 lsb (ideal value) = [v] avrh C avrl 1024
mb91101/mb91101a 96 n reference data 1. operating frequency vs. i cc characteristics 2. v cc vs. i cc characteristics 90 80 70 60 50 40 30 20 10 0 0 1020304050 (v cc ) 3.6 v 3.3 v 3.0 v 2.7 v i cc (ma) 90 80 70 60 50 40 30 20 10 0 0 1020304050 (v cc ) 4.5 v to 5.5 v i cc (ma) f (mhz) f (mhz) internal dc - dc regulator is not used (v cc = 3 v) internal dc - dc regulator is used (v cc = 5 v) operating conditions : source oscillation 12.5 mhz (crystal), pll is used (50 m, 25 m, 12.5 m) gear : cpu = 1/1, peripherals = 1/1 (doubler is used for 50mhz, gear peripherals = 1/2) v cc (v) v cc (v) 18 16 14 14 10 8 4 2 0 3.3 3.0 2.7 3.6 12 18 16 14 14 10 8 4 2 0 5.0 4.5 5.5 12 i cc (ma) icc (ma) gear : 1/1 gear : 1/2 gear : 1/4 gear : 1/8 gear : 1/8 (pll : off) gear : 1/1 gear : 1/2 gear : 1/4 gear : 1/8 gear : 1/8 (pll : off) internal dc - dc regulator is not used (v cc = 3 v) internal dc - dc regulator is used (v cc = 5 v) operating conditions : source oscillation 12.5 mhz (crystal), divide-by-2 input, pll : on gear : cpu = peripherals
97 mb91101/mb91101a n instructions (165 instructions) 1. how to read instruction set summary (1) names of instructions instructions marked with * are not included in cpu specifications. these are extended instruction codes added/extended at assembly language levels. (2) addressing modes specified as operands are listed in symbols. refer to 2. addressing mode symbols for further information. (3) instruction types (4) hexa-decimal expressions of instructions (5) the number of machine cycles needed for execution a: memory access cycle and it has possibility of delay by ready function. b: memory access cycle and it has possibility of delay by ready function. if an object register in a ld operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: if an immediately following instruction operates to an object of r15, ssp or usp in read/write mode or if the instruction belongs to instruction format a group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: if an immediately following instruction refers to mdh/mdl, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. for a, b, c and d, minimum execution cycle is 1. (6) change in flag sign ? flag change c : change C : no change 0:clear 1:set ? flag meanings n : negative flag z:zero flag v:over flag c:carry flag (7) operation carried out by instruction mnemonic type op cyc nzvc operation remarks add rj, ri * add #s5, ri , , a c , , a6 a4 , , 1 1 , , cccc cccc , , ri + rj ? ri ri + s5 ? ri , , (1) (2) (3) (4) (5) (6) (7)
mb91101/mb91101a 98 2. addressing mode symbols ri : register direct (r0 to r15, ac, fp, sp) rj : register direct (r0 to r15, ac, fp, sp) r13 : register direct (r13, ac) ps : register direct (program status register) rs : register direct (tbr, rp, ssp, usp, mdh, mdl) cri : register direct (cr0 to cr15) crj : register direct (cr0 to cr15) #i8 : unsigned 8-bit immediate (C128 to 255) note: C128 to C1 are interpreted as 128 to 255 #i20 : unsigned 20-bit immediate (C0x80000 to 0xfffff) note: C0x7ffff to C1 are interpreted as 0x7ffff to 0xfffff #i32 : unsigned 32-bit immediate (C0x80000000 to 0xffffffff) note: C0x80000000 to C1 are interpreted as 0x80000000 to 0xffffffff #s5 : signed 5-bit immediate (C16 to 15) #s10 : signed 10-bit immediate (C512 to 508, multiple of 4 only) #u4 : unsigned 4-bit immediate (0 to 15) #u5 : unsigned 5-bit immediate (0 to 31) #u8 : unsigned 8-bit immediate (0 to 255) #u10 : unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : unsigned 8-bit direct address (0 to 0xff) @dir9 : unsigned 9-bit direct address (0 to 0x1fe, multiple of 2 only) @dir10 : unsigned 10-bit direct address (0 to 0x3fc, multiple of 4 only) label9 : signed 9-bit branch address (C0x100 to 0xfc, multiple of 2 only) label12 : signed 12-bit branch address (C0x800 to 0x7fc, multiple of 2 only) label20 : signed 20-bit branch address (C0x80000 to 0x7ffff) label32 : signed 32-bit branch address (C0x80000000 to 0x7fffffff) @ri : register indirect (r0 to r15, ac, fp, sp) @rj : register indirect (r0 to r15, ac, fp, sp) @(r13, rj) : register relative indirect (rj: r0 to r15, ac, fp, sp) @(r14, disp10) : register relative indirect (disp10: C0x200 to 0x1fc, multiple of 4 only) @(r14, disp9) : register relative indirect (disp9: C0x100 to 0xfe, multiple of 2 only) @(r14, disp8) : register relative indirect (disp8: C0x80 to 0x7f) @(r15, udisp6) : register relative (udisp6: 0 to 60, multiple of 4 only) @ri+ : register indirect with post-increment (r0 to r15, ac, fp, sp) @r13+ : register indirect with post-increment (r13, ac) @sp+ : stack pop @Csp : stack push (reglist) : register list
99 mb91101/mb91101a 3. instruction types add, addn, cmp, lsl, lsr and asr instructions only msb type a ri lsb rj op type b type c type *c type d type e type f 16 bits 4 4 8 op i8/o8 ri 484 ri u4/m4 op 4 4 8 op s5/u5 ri 754 op u8/rel8/dir/reglist 88 op sub-op ri 844 op rel11 511
mb91101/mb91101a 100 4. detailed description of instructions ? add/subtract operation instructions (10 instructions) ? compare operation instructions (3 instructions) ? logical operation instructions (12 instructions) mnemonic type op cycle n z v c operation remarks add rj, ri * add #s5, ri add #i4, ri add2 #i4, ri a c c c a6 a4 a4 a5 1 1 1 1 cccc cccc cccc cccc ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension addc rj, ri a a7 1 cccc ri + rj + c ? ri add operation with sign addn rj, ri * addn #s5, ri addn #i4, ri addn2 #i4, ri a c c c a2 a0 a0 a1 1 1 1 1 CCCC CCCC CCCC CCCC ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension sub rj, ri a ac 1 cccc ri C rj ? ri subc rj, ri a ad 1 cccc ri C rj C c ? ri subtract operation with carry subn rj, ri a ae 1 C C C C ri C rj ? ri mnemonic type op cycle n z v c operation remarks cmp rj, ri * cmp #s5, ri cmp #i4, ri cmp2 #i4, ri a c c c aa a8 a8 a9 1 1 1 1 cccc cccc cccc cccc ri C rj ri C s5 ri + extu (i4) ri + extu (i4) msb is interpreted as a sign in assembly language zero-extension sign-extension mnemonic type op cycle n z v c operation remarks and rj, ri and rj, @ri andh rj, @ri andb rj, @ri a a a a 82 84 85 86 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri & = rj (ri) & = rj (ri) & = rj (ri) & = rj word word half word byte or rj, ri or rj, @ri orh rj, @ri orb rj, @ri a a a a 92 94 95 96 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri | = rj (ri) | = rj (ri) | = rj (ri) | = rj word word half word byte eor rj, ri eor rj, @ri eorh rj, @ri eorb rj, @ri a a a a 9a 9c 9d 9e 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri ^ = rj (ri) ^ = rj (ri) ^ = rj (ri) ^ = rj word word half word byte
101 mb91101/mb91101a ? bit manipulation arithmetic instructions (8 instructions) *1: assembler generates bandl if result of logical operation u8&0x0f leaves an active (set) bit and generates bandh if u8&0xf0 leaves an active bit. depending on the value in the u8 format, both bandl and bandh may be generated. *2: assembler generates borl if result of logical operation u8&0x0f leaves an active (set) bit and generates borh if u8&0xf0 leaves an active bit. *3: assembler generates beorl if result of logical operation u8&0x0f leaves an active (set) bit and generates beorh if u8&0xf0 leaves an active bit. ? add/subtract operation instructions (10 instructions) *1: divos, div1 32, div2, div3 and div4s are generated. a total instruction code length of 72 bytes. *2: divou and div1 32 are generated. a total instruction code length of 66 bytes. mnemonic type op cycle n z v c operation remarks bandl #u4, @ri (u4: 0 to 0f h ) bandh #u4, @ri (u4: 0 to 0f h ) * band #u8, @ri * 1 c c 80 81 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) & = (f0 h + u4) (ri) & = ((u4<<4) + 0f h ) (ri) & = u8 manipulate lower 4 bits manipulate upper 4 bits borl #u4, @ri (u4: 0 to 0f h ) borh #u4, @ri (u4: 0 to 0f h ) * bor #u8, @ri * 2 c c 90 91 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) | = u4 (ri) | = (u4<<4) (ri) | = u8 manipulate lower 4 bits manipulate upper 4 bits beorl #u4, @ri (u4: 0 to 0f h ) beorh #u4, @ri (u4: 0 to 0f h ) * beor #u8, @ri * 3 c c 98 99 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) ^ = u4 (ri) ^ = (u4<<4) (ri) ^ = u8 manipulate lower 4 bits manipulate upper 4 bits btstl #u4, @ri (u4: 0 to 0f h ) btsth #u4, @ri (u4: 0 to 0f h ) c c 88 89 2 + a 2 + a 0cCC ccC C (ri) & u4 (ri) & (u4<<4) te s t l o w e r 4 b i t s test upper 4 bits mnemonic type op cycle n z v c operation remarks mul rj, ri mulu rj, ri mulh rj, ri muluh rj, ri a a a a af ab bf bb 5 5 3 3 cccC cccC ccC C ccC C rj ri ? mdh, mdl rj ri ? mdh, mdl rj ri ? mdl rj ri ? mdl 32-bit 32-bit = 64-bit unsigned 16-bit 16-bit = 32-bit unsigned divos ri divou ri div1 ri div2 ri div3 div4s * div ri * 1 * divu ri * 2 e e e e e e 97 C 4 97 C 5 97 C 6 97 C 7 9f C 6 9f C 7 1 1 d 1 1 1 C C CCCC CCCC CcCc CcCc CCCC CCCC CcCc CcCc mdl/ri ? mdl, mdl%ri ? mdh mdl/ri ? mdl, mdl%ri ? mdh step calculation 32-bit/32-bit = 32-bit unsigned
mb91101/mb91101a 102 ? shift arithmetic instructions (9 instructions) ? immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) *1: if an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. if an immediate value contains relative value or external reference, assembler selects i32. ? memory load instructions (13 instructions) note: the relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: mnemonic type op cycle n z v c operation remarks lsl rj, ri * lsl #u5, ri lsl #u4, ri lsl2 #u4, ri a c c c b6 b4 b4 b5 1 1 1 1 ccCc ccCc ccCc ccCc ri<>rj ? ri ri>>u5 ? ri ri>>u4 ? ri ri>>(u4 + 16) ? ri logical shift asr rj, ri * asr #u5, ri asr #u4, ri asr2 #u4, ri a c c c ba b8 b8 b9 1 1 1 1 ccCc ccCc ccCc ccCc ri>>rj ? ri ri>>u5 ? ri ri>>u4 ? ri ri>>(u4 + 16) ? ri logical shift mnemonic type op cycle n z v c operation remarks ldi: 32 #i32, ri ldi: 20 #i20, ri ldi: 8 #i8, ri * ldi # {i8 | i20 | i32}, ri * 1 e c b 9f C 8 9b c0 3 2 1 CCCC CCCC CCCC i32 ? ri i20 ? ri i8 ? ri {i8 | i20 | i32} ? ri upper 12 bits are zero- extended upper 24 bits are zero- extended mnemonic type op cycle n z v c operation remarks ld @rj, ri ld @(r13, rj), ri ld @(r14, disp10), ri ld @(r15, udisp6), ri ld @r15 +, ri ld @r15 +, rs ld @r15 +, ps a a b c e e e 04 00 20 03 07 C 0 07 C 8 07 C 9 b b b b b b 1 + a + b CCCC CCCC CCCC CCCC CCCC CCCC cccc (rj) ? ri (r13 + rj) ? ri (r14 + disp10) ? ri (r15 + udisp6) ? ri (r15) ? ri, r15 + = 4 (r15) ? rs, r15 + = 4 (r15) ? ps, r15 + = 4 rs: special-purpose register lduh @rj, ri lduh @(r13, rj), ri lduh @(r14, disp9), ri a a b 05 01 40 b b b CCCC CCCC CCCC (rj) ? ri (r13 + rj) ? ri (r14 + disp9) ? ri zero-extension zero-extension zero-extension ldub @rj, ri ldub @(r13, rj), ri ldub @(r14, disp8), ri a a b 06 02 60 b b b CCCC CCCC CCCC (rj) ? ri (r13 + rj) ? ri (r14 + disp8) ? ri zero-extension zero-extension zero-extension disp8 ? o8 = disp8 disp9 ? o8 = disp9>>1 disp10 ? o8 = disp10>>2 udisp6 ? u4 = udisp6>>2 each disp is a code extension. udisp4 is a 0 extension.
103 mb91101/mb91101a ? memory store instructions (13 instructions) note: the relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: ? transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) mnemonic type op cycle n z v c operation remarks st ri, @rj st ri, @(r13, rj) st ri, @(r14, disp10) st ri, @(r15, udisp6) st ri, @Cr15 st rs, @Cr15 st ps, @Cr15 a a b c e e e 14 10 30 13 17 C 0 17 C 8 17 C 9 a a a a a a a CCCC CCCC CCCC CCCC CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp10) ri ? (r15 + usidp6) r15 C = 4, ri ? (r15) r15 C = 4, rs ? (r15) r15 C = 4, ps ? (r15) word word word rs: special-purpose register sth ri, @rj sth ri, @(r13, rj) sth ri, @(r14, disp9) a a b 15 11 50 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp9) half word half word half word stb ri, @rj stb ri, @(r13, rj) stb ri, @(r14, disp8) a a b 16 12 70 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp8) byte byte byte mnemonic type op cycle n z v c operation remarks mov rj, ri mov rs, ri mov ri, rs mov ps, ri mov ri, ps a a a e e 8b b7 b3 17 C 1 07 C 1 1 1 1 1 c CCCC CCCC CCCC CCCC cccc rj ? ri rs ? ri ri ? rs ps ? ri ri ? ps transfer between general-purpose registers rs: special-purpose register rs: special-purpose register disp8 ? o8 = disp8 disp9 ? o8 = disp9>>1 disp10 ? o8 = disp10>>2 udisp6 ? u4 = udisp6>>2 each disp is a code extension. udisp4 is a 0 extension.
mb91101/mb91101a 104 ? non-delay normal branch instructions (23 instructions) notes: ? 2/1 in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? reti must be operated while s flag = 0. mnemonic type op cycle n z v c operation remarks jmp @ri e 97 C 0 2 C C C C ri ? pc call label12 call @ri f e d0 97 C 1 2 2 CCCC CCCC pc + 2 ? rp, pc + 2 + rel11 2 ? pc pc + 2 ? rp, ri ? pc ret e 97 C 2 2 C C C C rp ? pc return int #u8 d 1f 3+3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? i flag, 0 ? s flag, (tbr + 3fc C u8 4) ? pc inte e 9f C 3 3 + 3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? s flag, (tbr + 3d8 C u8 4) ? pc for emulator reti e 97 C 3 2 + 2a cccc (r15) ? pc, r15 C = 4, (r15) ? ps, r15 C = 4 bno label9 bra label9 beq label9 bne label9 bc label9 bnc label9 bn label9 bp label9 bv label9 bnv label9 blt label9 bge label9 ble label9 bgt label9 bls label9 bhi label9 d d d d d d d d d d d d d d d d e1 e0 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0
105 mb91101/mb91101a ? branch instructions with delays (20 instructions) notes: ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? delayed branch operation always executes next instruction (delay slot) before making a branch. ? instructions allowed to be stored in the delay slot must meet one of the following conditions. if the other instruction is stored, this device may operate other operation than defined. the instruction described 1 in the other cycle column than branch instruction. the instruction described a, b, c or d in the cycle column. mnemonic type op cycle n z v c operation remarks jmp:d @ri e 9f C 0 1 CCCC ri ? pc call:d label12 call:d @ri f e d8 9f C 1 1 1 CCCC CCCC pc + 4 ? rp, pc + 2 + rel11 2 ? pc pc + 4 ? rp, ri ? pc ret:d e 9f C 2 1 CCCC rp ? pc return bno:d label9 bra:d label9 beq:d label9 bne:d label9 bc:d label9 bnc:d label9 bn:d label9 bp:d label9 bv:d label9 bnv:d label9 blt:d label9 bge:d label9 ble:d label9 bgt:d label9 bls:d label9 bhi:d label9 d d d d d d d d d d d d d d d d f1 f0 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0
mb91101/mb91101a 106 ? direct addressing instructions note: the relations between the dir field of type-d in the instruction format and the assembler description from disp8 to disp10 are as follows: ? resource instructions (2 instructions) ? co-processor instructions (4 instructions) mnemonic type op cycle n z v c operation remarks dmov @dir10, r13 dmov r13, @dir10 dmov @dir10, @r13+ dmov @r13+, @dir10 dmov @dir10, @Cr15 dmov @r15+, @dir10 d d d d d d 08 18 0c 1c 0b 1b b a 2a 2a 2a 2a CCCC CCCC CCCC CCCC CCCC CCCC (dir10) ? r13 r13 ? (dir10) (dir10) ? (r13), r13 + = 4 (r13) ? (dir10), r13 + = 4 r15 C = 4, (dir10) ? (r15) (r15) ? (dir10), r15 + = 4 word word word word word word dmovh @dir9, r13 dmovh r13, @dir9 dmovh @dir9, @r13+ dmovh @r13+, @dir9 d d d d 09 19 0d 1d b a 2a 2a CCCC CCCC CCCC CCCC (dir9) ? r13 r13 ? (dir9) (dir9) ? (r13), r13 + = 2 (r13) ? (dir9), r13 + = 2 half word half word half word half word dmovb @dir8, r13 dmovb r13, @dir8 dmovb @dir8, @r13+ dmovb @r13+, @dir8 d d d d 0a 1a 0e 1e b a 2a 2a CCCC CCCC CCCC CCCC (dir8) ? r13 r13 ? (dir8) (dir8) ? (r13), r13 + + (r13) ? (dir8), r13 + + byte byte byte byte mnemonic type op cycle n z v c operation remarks ldres @ri+, #u4 c bc a C C C C (ri) ? u4 resource ri + = 4 u4: channel number stres #u4, @ri+ c bd a C C C C u4 resource ? (ri) ri + = 4 u4: channel number mnemonic type op cycle n z v c operation remarks copop #u4, #cc, crj, cri copld #u4, #cc, rj, cri copst #u4, #cc, crj, ri copsv #u4, #cc, crj, ri e e e e 9f C c 9f C d 9f C e 9f C f 2 + a 1 + 2a 1 + 2a 1 + 2a CCCC CCCC CCCC CCCC calculation rj ? cri crj ? ri crj ? ri no error traps disp8 ? dir + disp8 disp9 ? dir = disp9>>1 disp10 ? dir = disp10>>2 each disp is a code extension
107 mb91101/mb91101a ? other instructions (16 instructions) *1: in the addsp instruction, the reference between u8 of type-d in the instruction format and assembler description s10 is as follows. s10 ? s8 = s10>>2 *2: in the enter instruction, the reference between i8 of type-c in the instruction format and assembler description u10 is as follows. u10 ? u8 = u10>>2 *3: if either of r0 to r7 is specified in reglist, assembler generates ldm0. if either of r8 to r15 is specified, assembler generates ldm1. both ldm0 and ldm1 may be generated. *4: the number of cycles needed for execution of ldm0 (reglist) and ldm1 (reglist) is given by the following calculation; a (n C 1) + b + 1 when n is number of registers specified. *5: if either of r0 to r7 is specified in reglist, assembler generates stm0. if either of r8 to r15 is specified, assembler generates stm1. both stm0 and stm1 may be generated. *6: the number of cycles needed for execution of stm0 (reglist) and stm1 (reglist) is given by the following calculation; a n + 1 when n is number of registers specified. mnemonic type op cycle n z v c operation remarks nop e 9f C a 1 C C C C no changes andccr #u8 orccr #u8 d d 83 93 c c cccc cccc ccr and u8 ? ccr ccr or u8 ? ccr stilm #u8 d 87 1 CCCC i8 ? ilm set ilm immediate value addsp #s10 * 1 d a3 1 CCCC r15 + = s10 add sp instruction extsb ri extub ri extsh ri extuh ri e e e e 97 C 8 97 C 9 97 C a 97 C b 1 1 1 1 CCCC CCCC CCCC CCCC sign extension 8 ? 32 bits zero extension 8 ? 32 bits sign extension 16 ? 32 bits zero extension 16 ? 32 bits ldm0 (reglist) ldm1 (reglist) * ldm (reglist) * 3 d d 8c 8d * 4 * 4 C CCCC CCCC CCCC (r15) ? reglist, r15 increment (r15) ? reglist, r15 increment (r15 + +) ? reglist, load-multi r0 to r7 load-multi r8 to r15 load-multi r0 to r15 stm0 (reglist) stm1 (reglist) * stm2 (reglist) * 5 d d 8e 8f * 6 * 6 C CCCC CCCC CCCC r15 decrement, reglist ? (r15) r15 decrement, reglist ? (r15) reglist ? (r15 + +) store-multi r0 to r7 store-multi r8 to r15 store-multi r0 to r15 enter #u10 * 2 d 0f 1+a CCCC r14 ? (r15 C 4), r15 C 4 ? r14, r15 C u10 ? r15 entrance processing of function leave e 9f C 9 b C C C C r14 + 4 ? r15, (r15 C 4) ? r14 exit processing of function xchb @rj, ri a 8a 2a C C C C ri ? temp, (rj) ? ri, temp ? (rj) for semafo management byte data
mb91101/mb91101a 108 ? 20-bit normal branch macro instructions *1: call20 (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call @ri *2: bra20 (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp @ri *3: bcc20 (beq20 to bhi20) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp @ri false: mnemonic operation remarks * call20 label20, ri next instruction address ? rp, label20 ? pc ri: temporary register * 1 * bra20 label20, ri * beq20 label20, ri * bne20 label20, ri * bc20 label20, ri * bnc20 label20, ri * bn20 label20, ri * bp20 label20, ri * bv20 label20, ri * bnv20 label20, ri * blt20 label20, ri * bge20 label20, ri * ble20 label20, ri * bgt20 label20, ri * bls20 label20, ri * bhi20 label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
109 mb91101/mb91101a ? 20-bit delayed branch macro instructions *1: call20:d (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call:d @ri *2: bra20:d (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp:d @ri *3: bcc20:d (beq20:d to bhi20:d) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp:d @ri false: mnemonic operation remarks * call20:d label20, ri next instruction address + 2 ? rp, label20 ? pc ri: temporary register * 1 * bra20:d label20, ri * beq20:d label20, ri * bne20:d label20, ri * bc20:d label20, ri * bnc20:d label20, ri * bn20:d label20, ri * bp20:d label20, ri * bv20:d label20, ri * bnv20:d label20, ri * blt20:d label20, ri * bge20:d label20, ri * ble20:d label20, ri * bgt20:d label20, ri * bls20:d label20, ri * bhi20:d label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
mb91101/mb91101a 110 ? 32-bit normal macro branch instructions *1: call32 (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call @ri *2: bra32 (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp @ri *3: bcc32 (beq32 to bhi32) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp @ri false: mnemonic operation remarks * call32 label32, ri next instruction address ? rp, label32 ? pc ri: temporary register * 1 * bra32 label32, ri * beq32 label32, ri * bne32 label32, ri * bc32 label32, ri * bnc32 label32, ri * bn32 label32, ri * bp32 label32, ri * bv32 label32, ri * bnv32 label32, ri * blt32 label32, ri * bge32 label32, ri * ble32 label32, ri * bgt32 label32, ri * bls32 label32, ri * bhi32 label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
111 mb91101/mb91101a ? 32-bit delayed macro branch instructions *1: call32:d (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call:d @ri *2: bra32:d (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp:d @ri *3: bcc32:d (beq32:d to bhi32:d) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp:d @ri false: mnemonic operation remarks * call32:d label32, ri next instruction address + 2 ? rp, label32 ? pc ri: temporary register * 1 * bra32:d label32, ri * beq32:d label32, ri * bne32:d label32, ri * bc32:d label32, ri * bnc32:d label32, ri * bn32:d label32, ri * bp32:d label32, ri * bv32:d label32, ri * bnv32:d label32, ri * blt32:d label32, ri * bge32:d label32, ri * ble32:d label32, ri * bgt32:d label32, ri * bls32:d label32, ri * bhi32:d label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
mb91101/mb91101a 112 n ordering information part number package remarks MB91101APFv 100-pin plastic lqfp (fpt-100p-m05) MB91101APF 100-pin plastic qfp (fpt-100p-m06)
113 mb91101/mb91101a n package dimensions (continued) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 0.50(.0197)typ .007 ?001 +.003 ?.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?004 +.008 ?.10 +0.20 1.50 .005 ?001 +.002 ?.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.50?.20(.020?008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.10?.10 (.004?004) (stand off) 0~10 lead no. (mouting height) dimensions in mm (inches) (fpt-100p-m05) 100-pin plastic lqfp
mb91101/mb91101a 114 (continued) note: the design may be modified changed without notice, contact to fujitsu sales division when using the device. c 1994 fujitsu limited f100008-3c-2 "a" "b" 0.10(.004) 0.53(.021)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.35(.486) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23.90?.40(.941?016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.13(.005) m 18.85(.742)ref 22.30?.40(.878?016) 1 30 31 50 51 80 81 100 0.25(.010) 0.30(.012) 0.65(.0256)typ 0.30?.10 (.012?004) lead no. 0.80?.20 (.031?008) 3.35(.132)max (mounting height) dimensions in mm (inches) (fpt-100p-m06) 100-pin plastic qfp
115 mb91101/mb91101a fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9907 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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